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Author: Ali abbass Zoraghchian (Company: highsym) (aliabbass)
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hi,i wrote a common bus(8 bit)with 4 registers and simple alu.registers 
r0,r1 and r3 inputs directly are connected to bus but r2 to alu out.the 
alu inputs are connected to r1 r2 outputs. all for registers output via 
muxs
are connected to bus and then consequently write the testbench for this 
code as follow:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- instead off two past sentenses you are authorized for using use 
ieee.numeric_std.all;
entity comm_bus is
    port(r0_in,r1_in,r3_in:inout std_logic_vector(0 to 7);
         --r2_in is not needed because we use from alu_out
         r0_out,r1_out,r2_out,r3_out:inout std_logic_vector(0 to 7);
         -- registers input & output must be identified inout and you 
dont have any way
         r0_clr,r1_clr,r2_clr,r3_clr:in std_logic;
         clk:in std_logic;
         r0_ld,r1_ld,r2_ld,r3_ld:in std_logic;
         opr:in std_logic_vector(2 downto 0);
         sel:in std_logic_vector(1 downto 0);
         bus_8bit:inout std_logic_vector(0 to 7));
end comm_bus;
-- for alu operation & selection mechanism we wana use from interface 
signals-----------
architecture behavioral of comm_bus is
signal alu_arm1,alu_arm2,alu_out:std_logic_vector(0 to 7);
--signal opr:std_logic_vector(2 downto 0);
--signal sel:std_logic_vector(1 downto 0);
begin
    process(clk)
        begin
            if (rising_edge(clk)) then
               if (r0_clr='0') then
                   r0_out<=(others=>'0');
               end if;
               if (r1_clr='0') then
                   r1_out<=(others=>'0');
               end if;
               if (r2_clr='0') then
                   r2_out<=(others=>'0');
               end if;
               if (r3_clr='0') then
                   r3_out<=(others=>'0');
               end if;
             end if;
     end process;
     process(clk)
         begin
             if (rising_edge(clk)) then
                if (r0_ld='1') then
                    r0_out<=r0_in;
                end if;
                if (r1_ld='1') then
                    r1_out<=r1_in;
                end if;
                if (r2_ld='1') then
                    r2_out<=alu_out;
                   --alu_out directly transfer to r2_out
                end if;
                if (r3_ld='1') then
                    r3_out<=r3_in;
                end if;
            end if;
      end process;
      r0_in<=bus_8bit;
      r1_in<=bus_8bit;
      r3_in<=bus_8bit;
      -- please attention r2 register input directly is connected to alu 
output
      process(sel)
          begin
              case sel is
                  when "00" =>
                      bus_8bit<=r0_out;
                  when "01" =>
                      bus_8bit<=r1_out;
                  when "10" =>
                      bus_8bit<=r2_out;
                  when "11" =>
                      bus_8bit<=r3_out;
                  when others => null;
               end case;
           end process;
           alu_arm1<=r1_out;
           alu_arm2<=r2_out;
           with opr select
              alu_out<=alu_arm1 + alu_arm2 when "000",
                       alu_arm1 - alu_arm2 when "001",
                       alu_arm1 and alu_arm2 when "010",
                       alu_arm1 or alu_arm2 when "011",
                       alu_arm1 nand alu_arm2 when "100",
                       alu_arm1 xor alu_arm2 when "101",
                       not alu_arm1 when "110",
                       not alu_arm2 when "111",
                       "--------" when others;
    end behavioral;
-----------------------------------------------------------------------
 library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
-----------------------------------------------------------------
entity top_module_comm_bus is
end top_module_comm_bus;
-----------------------------------------------------------------
architecture testbench of top_module_comm_bus is
constant t:time:=20 ns;
constant d:integer:=4;
constant dd:integer:=200;
signal r0_in,r1_in,r3_in:std_logic_vector(0 to 7);
signal r0_out,r1_out,r2_out,r3_out:std_logic_vector(0 to 7);
signal bus_8bit:std_logic_vector(0 to 7);
signal opr:std_logic_vector(2 downto 0);
signal sel:std_logic_vector(1 downto 0);
signal r0_clr,r1_clr,r2_clr,r3_clr:std_logic;
signal r0_ld,r1_ld,r2_ld,r3_ld:std_logic;
signal clk:std_logic;
begin
    uut: entity work.comm_bus(behavioral) port 
map(r0_in=>r0_in,r1_in=>r1_in,
     r3_in=>r3_in,r0_out=>r0_out,r1_out=>r1_out,r2_out=>r2_out,r3_out=>r3_out 
,
     r0_clr=>r0_clr,r1_clr=>r1_clr,r2_clr=>r2_clr,r3_clr=>r3_clr,
     r0_ld=>r0_ld,r1_ld=>r1_ld,r2_ld=>r2_ld,r3_ld=>r3_ld,clk=>clk,
     bus_8bit=>bus_8bit,
     opr=>opr,
     sel=>sel);
-- 20 ns clock is running forever
process
begin
    clk<='0';
    wait for t/2;
    clk<='1';
    wait for t/2;
end process;
--clear all of registers and then released them
--process
--begin
    --r0_clr<='0';
    --r1_clr<='0';
    --r2_clr<='0';
    --r3_clr<='0';
    --r0_ld<='0';
    --r1_ld<='0';
    --r2_ld<='0';
    --r3_ld<='0';
    --wait for d*t;
    --r0_clr<='1';
    --r1_clr<='1';
    --r2_clr<='1';
    --r3_clr<='1';
    --wait;
--end process;
r0_clr<='0','1' after t;
r1_clr<='0','1' after t;
r2_clr<='0','1' after t;
r3_clr<='0','1' after t;
r0_ld<='1','0' after t;
r1_ld<='1','0' after t;
r2_ld<='1','0' after t;
r3_ld<='1','0' after t;
-- now for example we have two numbers one of them in r1 and another one 
in r2
-- at first we add them and put result in r0 and again do some logical 
operation
-- on two registers r1 and r2 and this time put the result in r3
process
begin
    wait for d*d*t;
    bus_8bit<="10011100";
    wait for t;
    r1_ld<='1';
    wait for t;
    r1_ld<='0';
    opr<="000";
    wait for t;
    r2_ld<='1';
    wait for t;
    r2_ld<='0';
    wait for t;
    sel<="10";
    wait for t;
    sel<="--";
    r0_ld<='1';
    wait for t;
    r0_ld<='0';
    wait for t;
    opr<="010";
    wait for t;
    r2_ld<='1';
    wait for t;
    r2_ld<='0';
    wait for t;
    sel<="10";
    wait for t;
    sel<="--";
    wait for t;
    r3_ld<='1';
    wait for t;
    r3_ld<='0';
    wait for dd*d*t;
end process;
end testbench;

Author: Klakx (Guest)
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maybe there is more response if you also add a question :)

Additionally, format your code [vhdl]

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