Forum: FPGA, VHDL & Verilog How to create .coe file in Xilinx core generation

von Sarang S. (Company: Sasken) (sarang5s5s)

Rate this post
0 useful
not useful
I want to create a Single port ROM (in Block Memory generator core) and 
want to initialize memory by using .coe file. Can someone plz tell me 
how too create the .coe file ?

von Bit Bang Guy (Guest)

Rate this post
0 useful
not useful


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.