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Forum: FPGA, VHDL & Verilog How to create .coe file in Xilinx core generation


How to create .coe file in Xilinx core generation
von Sarang S. (Company: Sasken) (sarang5s5s)

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I want to create a Single port ROM (in Block Memory generator core) and 
want to initialize memory by using .coe file. Can someone plz tell me 
how too create the .coe file ?

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Re: How to create .coe file in Xilinx core generation
von Bit Bang Guy (Guest)

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Texteditor

http://www.xilinx.com/itp/xilinx10/isehelp/cgn_r_coe_file_syntax.htm

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