Forum: FPGA, VHDL & Verilog export port from altera qsys to verilog toplevel wrapper or fpga IO pins

von anonymous dude (Guest)

Rate this post
0 useful
not useful
with Altera QSys Tool, How to export a signal as an input or output pin 
to the fpga?

von anonymous dude (Guest)

Rate this post
0 useful
not useful
looks like you need to create a "new component" with the signals you 
want as your toplevel then bind a verilog model with required IO's to 
the "new component"... then add this new component your "System 
Contents" tab double click on the signals to export from the export 
column (column 4)...

If anybody can describe this better or knows a better or different way, 
then by all means write it here.


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.