export port from altera qsys to verilog toplevel wrapper or fpga IO pins

looks like you need to create a "new component" with the signals you 
want as your toplevel then bind a verilog model with required IO's to 
the "new component"... then add this new component your "System 
Contents" tab double click on the signals to export from the export 
column (column 4)...

If anybody can describe this better or knows a better or different way, 
then by all means write it here.