I am a student and I am working on a homework. Shortly, I will summary
shortly the hw's requirement. It said some thing like that: At first,
when counter goes from 0->7 then led 1 on; when the counter up to 8 then
led 2 on, up to 9 then led 3 on. Next, when the counter comes to 10, it
depends on a switch, if switch is on, led 4 on, if switch is off led 5
on. And if led 4 on, it still to be on until counter comes to 14 then
counter reset to 0 and comes back to first stage which means led 1 on.
And similarly, if led 5 on, it still to be on until counter comes to 22
then counter reset to 0 and comes back to first stage which means led 1.
The requirement is described by a lots of word but shortly it will be
like that after I design FSM for the problem. When I finish my code,
test bench runs OK but when I run on Altera DE1 board, it did not run
like my expectation. When the counter comes to 8,9,10 it runs nicely but
next when led 4 or led 5 on, it immediately comes back to stage 1 (led 1
on). Led 4 should be on 4 seconds or led 5 should be on 12 seconds
before come back to stage 1. In test bench, it waiting but in the board
nothing is waiting.
This is my code, hope you guys help me.
module controller(sw, clk, rst, led, y, Y); //This is top level module
input sw, clk, rst;
output [4:0] led;
output reg [2:0]y=0,Y=0; //y: present state; Y: next state
first of all, welcome to the fantastic world of FPGA...
As you could see, simulating (unrouted RTL code) will show you the ideal
behaviour before partitioning your logic in rather small alements with
sublightspeed limited routing delays.
For this you will be never able to come in the situation you found on
I will give you some idears and you might try to fix your Logic for
yourself (at least try to do so for educational purposes)...
1) This might not be a real problem in this design, but it is bad coding
Never use a clock which is generated by a simple clock devider.
Better to use a DCM or PLL element in your FPGA.
Best is to modify and use your clock devider as an Clock Enable
2) You are using an external input (sw) which is asynchronly to your
logic. Other than in a simple RTL simulation, every littly cell of logic
will se this input (switching) at a different time (in respect to the
clock edge). So first of all synchronize your sw to the clock you are
using, and use the resulting signal in your logic.
3) Last and most important here, you first always Block is completly
asynchronous. So remember, every single bit of your state reg and count
bits will arive at a different time at your logic in your real fpga.
Synchronizing to clock will help you out...