Hey guys, I am experimenting with UDP on my Arty FPGA board.(https://reference.digilentinc.com/arty) After some fiddeling the transmitting of data to my laptop already works. My problem now is that the rx_data bus does not seem to give me other data than "0000" and "1111". I have also connected the rx_dv to an led and I see it blinking so I assume there should be more useful data than just these two values on the bus. I am also sure that there are packets sent. I see them in wireshark. Did you guys already have a similar problem and can point me in a general direction? Greetings, Jonas
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How did you check the rx data? Also with LED? Or with chipscope? Duke
Hey Duke, Thanks for your answer. I checked it by letting an led light up permanently after a nibble that was not "0000" was found. I have an LED that is connected to rx_dv and that blinks. I was not aware that chipscope exists. I will try to learn more about it and use it, but for now I have implemented a UDP Sender that successfully sends data, that I also see in Wireshark. I now have connected the rx_dv to tx_en and rxd to txd and update these on falling_edge(tx_clk). This successfully bounces back all packets, but instead of any data, every nibble is "0000". I have attached a Wireshark save file of two example packets sent to the FPGA and the two answers. The ethernet frame checksum is wrong because I set the UDP packet length to 18. I will try to fix this with an automated counter, but it should make no difference.
I have now also debugged it with the Vivado ILA. I have registered a trigger to rxd not being "0000" and it never triggers. When I register a trigger to rx_dv it triggers normally. This is really weird. Do you guys have any ideas? Jonas
Did you use the correct pins for rxd? How fast is your ethernet? How fast is your fpga system clock? Duke
Thanks a lot for your help. Yes I used the correct pins. The .xdc comes directly from the vendor. But this was a good tip. I checked the pins and saw that the rdx pins were declared at OUT in the elaborated design. I do not know why, but I declared the rxd port as a buffer instead of a in port in the VHDL. I now declared it as an in port and it works like a charm. I now feel a bit stupid, but also know more about FPGAs. :D Jonas
Hi Jonas, i know its been a while, but is there any chance you could tell me how you implemented the Receiving part or where you got it from ? I've been searching for days and struggle with finding a code the makes receiving udp packets possible, i also use the Arty Board at 100MHz and send UDP Packets regards Waldi
I second that request - if you have UDP VHDL/Verilog code, or found it online, can you post the source? I tried running the Vivado example code but it's not designed for Arty. Thank you, Rick
Waldi, Were you able to find any UDP code for the Arty? I'm looking as well.
To others finding this in the future this code works right out of the box - it's great (sends via UDP, no receive built in, and there's a Gigabit version on GitHub as well). https://github.com/hamsternz/ArtyEtherentTX
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