EmbDev.net

Forum: FPGA, VHDL & Verilog square root verilog


square root verilog
von Julia (Guest)

Rate this post
• ▲ useful
▼ not useful 
Hi everyone,

I really need your helps on how to implement square root in verilog hdl.

Thank you

Report post Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Re: square root verilog
von CJU (Guest)

Rate this post
• ▲ useful
▼ not useful 
Hello,

http://www.lbebooks.com/downloads/exportal/Verilog_NEXYS_Example24.pdf

Good luck, Julia.

Report post Edit Delete Quote selected text Reply Reply with quote
Re: square root verilog
von expert (Guest)

Rate this post
• ▲ useful
▼ not useful 
does anybod have a similar source fpr VHDL code?

Report post Edit Delete Quote selected text Reply Reply with quote
Re: square root verilog
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

Rate this post
• ▲ useful
▼ not useful 
Try that:
http://www.lothar-miller.de/s9y/archives/73-Wurzel-in-VHDL.html

: Edited by Moderator
Report post Edit Delete Quote selected text Reply Reply with quote
Re: square root verilog
von Jürgen S. (engineer)

Rate this post
• ▲ useful
▼ not useful 
Those requiring an ultra fast square root with look ahead architecture 
may contact me. It runs n inputs bits at l bits latency given by:

l = 7 + n / 2 and thus is suitable starting from n>30 bits.

It has an n.n/2 vector result.

Artix 7 tested:

sqrt(64 bits) -> 32.16 Bits result within 39 ccs @ 200MHz.

Report post Edit Delete Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view
Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
No account? Register here.