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Forum: FPGA, VHDL & Verilog square root verilog


Author: Julia (Guest)
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Hi everyone,

I really need your helps on how to implement square root in verilog hdl.

Thank you

Author: CJU (Guest)
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Author: expert (Guest)
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does anybod have a similar source fpr VHDL code?

Author: Lothar M. (lkmiller) (Moderator)
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: Edited by Moderator
Author: Jürgen S. (engineer)
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Those requiring an ultra fast square root with look ahead architecture 
may contact me. It runs n inputs bits at l bits latency given by:

l = 7 + n / 2 and thus is suitable starting from n>30 bits.

It has an n.n/2 vector result.

Artix 7 tested:

sqrt(64 bits) -> 32.16 Bits result within 39 ccs @ 200MHz.

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