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Forum: FPGA, VHDL & Verilog CAN controller implementation using FPGA


von CJU (Guest)


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Hello, everyone.

First, i'm sorry. Because of, I cant speak english well.

I have some ploblem about my project.

I should design CAN controller using Verilog HDL in FPGA.

But, any web-site doesn't have that information.

I got the CAN verilog code in OpenCore.

But, I cant understand OpenCore code.

It explain only block diagram....

If you know about that.... help me please..

Thank you very much.

von CJU (Guest)


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And, I used xilinx ISE tool and simulator

von mh (Guest)


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Unfortunately CAN specs are ISO standard and not freely available (any 
more).
At Bosch you can still find some documents --> 
http://www.bosch-semiconductors.de/en/automotive_electronics/ip_modules/can_literature_2.html

What is exactly your problem? The CAN bus or Verilog?

If you shall design an CAN IP core, you should do that based on the 
specification not based on another implementation (with missing 
documentation and questionable quality).
The person that gave you the task should also provide access to the 
corresponding specification (ISO11898*).

von CJU (Guest)


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First, Thank you very much, your reply.

I have to make CAN controller using Verilog HDL Code. And, 
implementation in FPGA.

So, I downloaded the code in OpenCore and simulated using Xilinx ISE 
tool.
But, I cant find output and input... in simulation.. cant understand 
that code.

I need some code(CAN controller in Verilog) or CAN block example(Verilog 
code.. bit stuffing, CRC...etc)

If you know the solution about my ploblem, tell me please..

Thank you!

von Tim (Guest)


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Hi,

I had the same problem a while ago. I also used the code by 
opencores.org but Vivado instead of ISE.
What exactly do you mean with input and outputs? You have a Wishbone bus 
as input (registers are the same as SJA1000 controller) and CAN-rx and 
tx as output.

I recently posted my solution: 
http://osdr.org/can-ip-core-implementation-on-xilinx-zynq-platform/

Tim

von CJU (Guest)


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Hello, Tim. Thank you your reply.

First, input and output mean just signal in verilog
(ex, CAN module (
   input [15:0] in,
   output reg [15:0] out
)...

I cant find that in Opencore codes.

Did you design the CAN controller in FPGA?
( using Opencore code or another method...)

I have a ZYNQ board for FPGA design.
If you implemented CAN controller in FPGA, Can you help me?

And, also Can I know your email address?

If i can know your email address, send ma a message to 
jeongminwoo7@naver.com.

Thank you very much, Tim.

von Jk (Guest)


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Hi everyone

Can anyone share me the block design codes,I am having the same problem 
as mentioned above.

jkmenon94@gmail.com

von asdfa (Guest)


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If you find one please shhare with me brother

von https://www.b2kopi.com/product/detail.aspx?id=4856 (Guest)


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