AK Aymen K. (aymen) OP 2015-11-16 23:13 #4352939 Rate this post • ▲ useful ▼ not useful Hi all, What is this constraint: Translate on and Translate off: the Verilog code between Translate on and Translate off is ignored for synthesis. Thank you Reply Quote Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Report post
LM Lothar M. (lkmiller) Moderator (Company: Titel) 2015-11-17 06:20 #4353069 Rate this post • ▲ useful ▼ not useful What is unclear with this statement? "synthesis" means "implementaion to real hardware" Reply Quote Edit Delete Report post