Forum: FPGA, VHDL & Verilog logical processor, problem with connectivity between bits and block diagram

von Tm P. (cyanide)

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Disclaimer: I'm newbie in vhdl.

I'm working on an assignment that aims for creating a logical processor 
that makes bit logical operations on 8-bit operands. Unfortunately I'm 
lost when it comes to connecting bits of the project and I can't move 
forward due to that, as vhdl is a dark territory for me.

Could someone help me connecting the parts of this processor so I can 
move forward?

Below blocks with IO and their purpose described:

List of blocks:

1. Whole processor block:
CLK - clock
RST - reset
EXEC - execution of calculations
LOAD_A - load into Reg_A particular bit from DATA
LOAD_B - load into Reg_B particular bit from DATA
DATA <7:0>
Seg <6:0> - seven-segment display (with active '0')
Anod <3:0> - bits for another 4 displays working similarly to Seg
LED <7:0> - bits for diodes' steering

2. steering block:
Exec is a rising edge that starts the counting sequence and all the data 
thrown at Exec while its working is being ignored.
random variable that, based on set logic, decides when to load data from 
DATA and when to shift what's loaded on registers

3. register_block
includes 2x 8-bit register, named REGISTER_A and REGISTER_B
outs: LED
Here i've also got some problems with creating proper logic for these 
registers; they're both shift registers and i know how to set it up, but 
I have no idea how to program that they send 1 bit of data starting from 
the youngest bit when EXEC is active.

4. calc_block
Here's another problem - out of the blue in the description of my task 
i've got info that this block executes logical operation based on F<2:0> 
(I've got necessary data to fill F with it) but it also says its the 
result of L_AB and i don't know whether i should take it as the result 
of shifting data between registers or not.

5. Router
It returns info to the register_block - I have no idea how to implement 
this in my project. The whole description goes like that: it takes 
signals A and B and the result of L_AB and sends to register_block 
signals New_A and New_B based on the selection of R<1:0>

6. Display
It's just a standard seven-seg display with a dynamic display for 
thousands, hundreds, tens and ones.

Summing up, I'm getting lost around while working on points 3 to 5.

Thanks in advance, I believe that just a bit of explanation for points 3 
to 5 and some kind of a block diagram presenting connections between 
particular blocks would be more than enough for me to finish that 

: Edited by User


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