Hi, I am getting an error : There are no HDL sources in file set 'sources_1'. Please use the Add Sources command. The code file and the error screenshot are attached. Please let me know what could be the cause of error and how to remove it. Thanks and regards, Rohan Narkhede
Just to add, I am using Xilinx Vivado for code compilation.
The screenshot shows syntax error. You have to fix them first.
What does vivado complain about. If you click on the "syntax error files" you should see in which line your problem is.
Hi, The syntax error it shows is at line 42 and 44. (Please see the new screenshot attached with this reply). I don't understand what is the syntax error here, as I have ended the process and ended the architecture - reg_arch like normal syntax. Thanks an dregards, Rohan Narkhede
There is an "end if;" missing right in front of end process!
Thank you so much derLars!!
If you use tabs consequently, it is very easy to observe, like:
entity reg is port( clk : in std_logic; ... reset : in std_logic ); end entity reg; architecture reg_arch of reg is signal r_reg : std_logic_vector(1 downto 0); ... begin process(clk) begin if reset = '1' then ... elsif rising_edge(clk) then if ctrl0 = '0' ... then ... elsif ... ... elsif ... ... end if; <<<<<<<<<<<<<<<<<<< here is something obviously missing! end process; dout <= r_reg; end architecture;