There are no HDL sources in file set 'sources_1'. Please use the Add Sources command.

Just to add, I am using Xilinx Vivado for code compilation.

The screenshot shows syntax error. You have to fix them first.

What does vivado complain about. If you click on the "syntax error 
files" you should see in which line your problem is.

Hi,

The syntax error it shows is at line 42 and 44. (Please see the new 
screenshot attached with this reply). I don't understand what is the 
syntax error here, as I have ended the process and ended the 
architecture - reg_arch like normal syntax.

Thanks an dregards,
Rohan Narkhede

There is an "end if;" missing right in front of end process!

Thank you so much derLars!!

If you use tabs consequently, it is very easy to observe, like:

1

entity reg is

2

  port(

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    clk     : in  std_logic;

4

    ...

5

    reset   : in  std_logic

6

  );

7

end entity reg;

8

9

architecture reg_arch of reg is

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  signal r_reg : std_logic_vector(1 downto 0);

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  ...

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begin

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  process(clk)

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  begin

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    if reset = '1' then

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    ...

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    elsif rising_edge(clk) then

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      if ctrl0 = '0' ... then

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      ...

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      elsif ...

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      ...

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      elsif ...

23

      ...

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      end if;

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      <<<<<<<<<<<<<<<<<<< here is something obviously missing!

26

  end process;

27

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  dout <= r_reg;

29

30

end architecture;