Hi I have a MachXO2 Device LCMXO2-7000HE. In my design I have the Lattice Mico8 softcore with Wishbone interface (downloaded Reference design). Then I have an EFB block where I want to use the UFM. There are other peripherials to the controller such as UART and they all work fine. But I don't manage to get the communication going with the UFM. Maybe I am doing something wrong with the protocol or timing. Can anyone provide me a reference code where I can see how the communication with the UFM via Wishbone is done. Any help appreciated. Sincerely
How to access the UFM you will find in this docoument page 73 ff http://www.latticesemi.com/view_document?document_id=46300
Thanks I actually studied that document already, but I am still not able to establish communication. That is why I ask if someone can provide me a working reference code either in C or assembler. But maybe you are right, I have to analyze the wishbone signals with an logic analyzer to see whether I meet the timings exactly as described in this document. Sincerely
Sorry i can't provide a sample for the Mico8, only general help. (i have used a simple FSM to read one page in my projects) Don't worry about the WB timing, the Mico8 core should do it correctly.
enable the configuration interface 0x80 -> 0x70 Open frame 0x74 -> 0x71 Cmd 0x08 -> 0x71 0x00 -> 0x71 0x00 -> 0x71 0x00 -> 0x70 Close frame WAIT 5 usec. Set page address 0x80 -> 0x70 0xB4 -> 0x71 0x00 -> 0x71 0x00 -> 0x71 0x00 -> 0x71 0x40 -> 0x71 0x00 -> 0x71 PageH -> 0x71 PageL -> 0x71 0x00 -> 0x70 read page 0x80 -> 0x70 0xCA -> 0x71 // here i have a small delay, not sure why 0x10 -> 0x71 0x00 -> 0x71 0x01 -> 0x71 0x73 -> Byte 0 0x73 -> Byte 1 ... 0x73 -> Byte 15 0x00 -> 0x70 disable config interface 0x80 -> 0x70 0x26 -> 0x71 0x00 -> 0x71 0x00 -> 0x71 0x80 -> 0x70 bypass 0x80 -> 0x70 0xFF -> 0x71 0xFF -> 0x71 0xFF -> 0x71 0xFF -> 0x71 0x80 -> 0x70
Thanks Lattice User My Assembler Code in Mico8 looks like this. Here I try to read the device ID as you suggested in the first post. When I read back the Device ID into register r17-20 I just got all zeros in it. I guess I have to analyse with a Logic Analyzer to see what is wrong. What is your opinion on this code
movi r15, FLASH ;Address of peripherial movi r11, CFGCR ;Port address Control Register 0x70 movi r13, CFGTXDR ;Port address Transmit Register 0x71 movi r9, CFGRXDR ;Port address Receive Register 0x73 movi r16, READ_DEVICE_ID ;Define Command 0xE0 movi r12, ZERO_OP ;Null Operand 0x00 movi r10, START_CMD ;Start Byte 0x80 movi r8, END_CMD ;Start Byte 0x00 ;Starte Kommando exporti r10,r11 ;Assert CFGCR[WBCE] ;Send Command exporti r16,r13 ;Send Command READ_DEVICE_ID exporti r12,r13 ;Send 0x00 operand 3x exporti r12,r13 exporti r12,r13 ;Read Device ID importi r17,r9 importi r18,r9 importi r19,r9 importi r20,r9 ;End Kommando exporti r8,r11 ;De-assert CFGCR[WBCE]
Hmmmm What memory modell are you using? For medium modell my version of the LM8 reference modell documents R13 as page pointer. From your code it looks like you are using R15.
Yes I have r15 and r14 as address register. I actually dont know what memory model I use, but it is the Reference Design RD1026 configured to 32 General Purpose registers.
: Edited by User
Which version of the Mico8 are you using? The latest 3.15 supports three meory modes: small: no page pointer medium: R13 is page pointer large: R13,R14,R15 is page pointer
I analyzed the Wishbone signals and surprise: the UFM block actually respond to the Read Device ID request. However, due to some timing issues the Mico8 importi implementation somehow is not able to capture the response from the UFM. My version of Mico8 is 3.1. I think I might have to update it to 3.15 as I infer by your comments. This might help. Ok see you later, maybe I can do it by Friday. Sincerely