Routing limits in fpga design

I would say for a simple switching function the number of IO pins is the 
limiting factor.

You'll need:
N inputs
N outputs
X lines for control, reset, clock

for very small FPGAs the number of logic units (LU) can also become a 
limiting factor. What a single LU actually can do depends strongly on 
the device type. But in worst case it is equivalent to a single one-bit 
2 to 1 mux. So you would roughly need 0.5*N*N LUs to do the job. But 
many FPGAs have special muxing features that simplify your special task 
and reduce the number of LUs required.

The only reliable way to find out if a design fits into a device is to 
actually try it by running a complete design process until the final 
binary file is created. This can be done without purchasing a device - 
"just" download the vendor's development toolchain, enter your design 
and run the compile and synthesis steps. As a result you will get a 
detailed report of how many resources in the device have been used. If 
only a small percentage of the device's resources is used a smaller 
device can be selected. If the design does not fit select a bigger 
device and restart the process.