Forum: FPGA, VHDL & Verilog Timing constrains wont affect path

von Noam (Guest)

Rate this post
0 useful
not useful
Hi everybody,

Im working on my first "big" vhdl project using quartus II 12.1 and 
Cyclone IV E device.

my problem is that im trying to improve paths timings all over my design 
but timing constrains have no affect over the paths im trying to 

i started with the long paths and reduced it down to 2 basic blocks and 

i know my describe is very general but i feel like im missing something 
very basic and simple.

found nothing online about this kind of problem and altera's timing 
guide was no help either.

to be more specific if it helps, my design is asynchronous (so no clock)
and im currently trying to use set_max_delay constrain to improve 
routing efficiency.

von Klakx (Guest)

Rate this post
0 useful
not useful
have you tried to apply Input and Output constraints? I dont know your 
circuit :-\


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.