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Generalize the module in verilog
Author: Muhammad Awais (fame313)
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i attached the v file of module Case2. i want to generalize this module. 
so that i can instantiate this module more times. and also any one can 
tell me that how i can make out put

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Re: Generalize the module in verilog
Author: Ale (Guest)
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Well,

did you simulate it ? what does it do ?...
There are some constant "inputs" and calculated "outputs", that would be 
a good starting point, don't you think so ?

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