EmbDev.net

Forum: FPGA, VHDL & Verilog Generalize the module in verilog


Generalize the module in verilog
Author: Muhammad A. (fame313)
Posted on:
Attached files:
Rate this post
0 ▲ useful
▼ not useful 
i attached the v file of module Case2. i want to generalize this module. 
so that i can instantiate this module more times. and also any one can 
tell me that how i can make out put

Report post Edit Move Thread sperren Anmeldepflicht aktivieren Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Re: Generalize the module in verilog
Author: Ale (Guest)
Posted on:
Rate this post
0 ▲ useful
▼ not useful 
Well,

did you simulate it ? what does it do ?...
There are some constant "inputs" and calculated "outputs", that would be 
a good starting point, don't you think so ?

Report post Edit Delete Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]



Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.