Verilog clock divider 50 MHz to 1 MHz

Hi, I'm trying to figure out how this clock diver works but I don't 
understand, why it's necessary to multiple clk_out by two. I'd be 
grateful for an explanation, thx.


// counter size calculation according to input and output frequencies
// parameter sys_clk = 50000000;  // 50 MHz system clock
// parameter clk_out = 1000000;  // 1 MHz clock output
// parameter max = sys_clk / (2*clk_out); // max-counter size


// always@(posedge Clk_in) begin
//   if (counter == max-1)
//     begin
//     counter <= 0;
//     Clk_out <= ~Clk_out;
//     end
//   else
//     begin
//     counter <= counter + 1'd1;
//     end
//   end
// endmodule