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Forum: FPGA, VHDL & Verilog vhdl test bench


von Rockyy S. (rockyy)


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1
 library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity test1 is
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    Port ( clk : in  STD_LOGIC;
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           input1 : in  STD_LOGIC;
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           input2 : in  STD_LOGIC;
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           output : out  STD_LOGIC);
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end test1;
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architecture Behavioral of test1 is
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  process(clk)
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begin
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      if (clk'event and clk='1') then
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        output <= input1 and input2;
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        end if;
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end process;
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end Behavioral;

For the above Program I have created a VHDL test bench like below
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY test IS
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END test;
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ARCHITECTURE behavior OF test IS 
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    -- Component Declaration for the Unit Under Test (UUT)
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    COMPONENT test1
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    PORT(
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         clk : IN  std_logic;
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         input1 : IN  std_logic;
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         input2 : IN  std_logic;
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         output : OUT  std_logic
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        );
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    END COMPONENT;
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   --Inputs
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   signal clk : std_logic := '0';
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   signal input1 : std_logic := '0';
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   signal input2 : std_logic := '0';
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     --Outputs
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   signal output : std_logic;
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   -- Clock period definitions
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   constant clk_period : time := 1 ns;
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BEGIN
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    -- Instantiate the Unit Under Test (UUT)
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   uut: test1 PORT MAP (
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          clk => clk,
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          input1 => input1,
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          input2 => input2,
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          output => output
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        );
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   -- Clock process definitions
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   clk_process :process
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   begin
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        clk <= '0';
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        wait for clk_period/2;
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        clk <= '1';
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        wait for clk_period/2;
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   end process;
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   -- Stimulus process
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   stim_proc: process
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   begin        
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      -- hold reset state for 100 ns.
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      wait for 10 ns;     
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        input1 <= '0';
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        input2 <= '0';
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        wait for 20 ns;
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        input1 <= '0';
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        input2 <= '1';
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        wait for 30 ns;
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        input1 <= '1';
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        input2 <= '0';
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        wait for 40 ns;
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        input1 <= '1';
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        input2 <= '1';
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   end process;
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END;

but after simulating the behavioural Model i am getting the value of
clk = U
input1 = U
input2 = U
output = U

I am very new to VHDL,Can any one let me know why I am getting U as 
value and not getting the Signal.Check the attach file for the output.

von Bitflüsterer (Guest)


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Declare your testbench, i.e. entity "test" as top level. Not "test1", 
which is the DUT (device under test) itself.
Another possibility is, that you marked the test1 entity when starting 
the simulator. Mark the testbench test instead, when starting 
simulation.

von Rockyy S. (rockyy)


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Thanks for the information its working

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