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Forum: FPGA, VHDL & Verilog vhdl test bench

von Rockyy S. (rockyy)

2014-08-11 11:29

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test_bench.png
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 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test1 is
    Port ( clk : in  STD_LOGIC;
           input1 : in  STD_LOGIC;
           input2 : in  STD_LOGIC;
           output : out  STD_LOGIC);
end test1;
architecture Behavioral of test1 is
  process(clk)
      if (clk'event and clk='1') then
        output <= input1 and input2;
        end if;
end process;
end Behavioral;


For the above Program I have created a VHDL test bench like below

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test IS
END test;
ARCHITECTURE behavior OF test IS 
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT test1
    PORT(
         clk : IN  std_logic;
         input1 : IN  std_logic;
         input2 : IN  std_logic;
         output : OUT  std_logic
    END COMPONENT;
   --Inputs
   signal clk : std_logic := '0';
   signal input1 : std_logic := '0';
   signal input2 : std_logic := '0';
     --Outputs
   signal output : std_logic;
   -- Clock period definitions
   constant clk_period : time := 1 ns;
    -- Instantiate the Unit Under Test (UUT)
   uut: test1 PORT MAP (
          clk => clk,
          input1 => input1,
          input2 => input2,
          output => output
   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;
   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
      wait for 10 ns;     
        input1 <= '0';
        input2 <= '0';
        wait for 20 ns;
        input1 <= '0';
        input2 <= '1';
        wait for 30 ns;
        input1 <= '1';
        input2 <= '0';
        wait for 40 ns;
        input1 <= '1';
        input2 <= '1';
   end process;


but after simulating the behavioural Model i am getting the value of
clk = U
input1 = U
input2 = U
output = U

I am very new to VHDL,Can any one let me know why I am getting U as 
value and not getting the Signal.Check the attach file for the output.

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Re: vhdl test bench

von Bitflüsterer (Guest)

2014-08-11 11:42

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Declare your testbench, i.e. entity "test" as top level. Not "test1", 
which is the DUT (device under test) itself.
Another possibility is, that you marked the test1 entity when starting 
the simulator. Mark the testbench test instead, when starting 
simulation.

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Re: vhdl test bench

von Rockyy S. (rockyy)

2014-08-11 12:20

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