1 | library IEEE;
|
2 | use IEEE.STD_LOGIC_1164.ALL;
|
3 | use IEEE.NUMERIC_STD.ALL;
|
4 |
|
5 | entity ALU is
|
6 | Port ( a : in STD_LOGIC_VECTOR;
|
7 | b : in STD_LOGIC_VECTOR;
|
8 | c_in : in STD_LOGIC;
|
9 | op : in STD_LOGIC_VECTOR;
|
10 | y : out STD_LOGIC_VECTOR;
|
11 | c_out : out STD_LOGIC;
|
12 | v : out STD_LOGIC;
|
13 | z : out STD_LOGIC;
|
14 | s : out STD_LOGIC );
|
15 | end ALU;
|
16 |
|
17 | architecture Behavioral of ALU is
|
18 | signal signal_a : STD_LOGIC_VECTOR (7 downto 0);
|
19 | signal signal_b : STD_LOGIC_VECTOR (7 downto 0);
|
20 | signal signal_c_in :STD_LOGIC;
|
21 | signal signal_output : STD_LOGIC_VECTOR (7 downto 0);
|
22 | signal signal_c_out : STD_LOGIC;
|
23 |
|
24 | signal unsigned_a, unsigned_b : unsigned (7 downto 0);
|
25 | signal unsigned_c_in : unsigned (0 downto 0);
|
26 | signal unsigned_output : unsigned (8 downto 0);
|
27 |
|
28 | signal not_a : STD_LOGIC_VECTOR (7 downto 0);
|
29 | signal a_and_b : STD_LOGIC_VECTOR (7 downto 0);
|
30 | signal a_or_b : STD_LOGIC_VECTOR (7 downto 0);
|
31 | signal a_xor_b : STD_LOGIC_VECTOR (7 downto 0);
|
32 |
|
33 | signal signal_y : STD_LOGIC_VECTOR (7 downto 0);
|
34 |
|
35 | begin
|
36 | signal_a <= NOT(a) when op = "0110"
|
37 | else a;
|
38 |
|
39 | signal_b <= NOT(b) when op = "1111"
|
40 | else "11111111" when op = "1110"
|
41 | else "00000000" when op = "0111" OR op = "0001"
|
42 | else b;
|
43 |
|
44 | signal_c_in <= '1' when op = "1111" OR op = "0001" OR op = "0110"
|
45 | else '0' when op = "1000"
|
46 | else c_in;
|
47 |
|
48 | not_a <= NOT(a);
|
49 |
|
50 | a_or_b <= a OR b;
|
51 |
|
52 | a_and_b <= a AND b;
|
53 |
|
54 | a_xor_b <= a XOR b;
|
55 |
|
56 | signal_y <= signal_output when op = "0000" else -- ADD
|
57 | signal_output when op = "1111" else -- SUB
|
58 | signal_output when op = "0110" else -- NEG
|
59 | signal_output when op = "0001" else -- INC
|
60 | signal_output when op = "1110" else -- DEC
|
61 |
|
62 | not_a when op = "0101" else
|
63 | a_or_b when op = "0111" else
|
64 | a_and_b when op = "0110" else
|
65 | a_xor_b when op = "1000" else
|
66 | "--------";
|
67 |
|
68 |
|
69 | unsigned_a <= unsigned(signal_a);
|
70 | unsigned_b <= unsigned(signal_b);
|
71 | unsigned_c_in(0) <= signal_c_in;
|
72 |
|
73 |
|
74 | unsigned_output <= ("0" & unsigned_a) + unsigned_b + unsigned_c_in;
|
75 | signal_output <= std_logic_vector(unsigned_output(7 downto 0));
|
76 | signal_c_out <= unsigned_output(8);
|
77 |
|
78 |
|
79 | y <= signal_y;
|
80 |
|
81 |
|
82 | v <= ((signal_a(7) AND signal_b(7) AND NOT signal_output(7))
|
83 | OR (NOT signal_a(7)AND NOT signal_b(7) AND signal_output(7)))
|
84 | when op = "0000" OR op = "1111" OR op = "0110" OR op = "0001" OR op = "1110"
|
85 | else '0';
|
86 |
|
87 | z <= '1' when signal_y = "00000000"
|
88 | else '0';
|
89 |
|
90 | s <= signal_y(7);
|
91 |
|
92 |
|
93 | c_out <= signal_c_out when op = "0000" OR op = "1111" OR op = "0110" OR op = "0001" OR op = "1110"
|
94 | else '0';
|
95 |
|
96 | end Behavioral;
|