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Forum: FPGA, VHDL & Verilog Basic ALU in VHDL


von VHDL_Help (Guest)


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Hi, first time posting! I'm trying to create a basic ALU. However, when 
I try to synthesize, I get the following errors:

ERROR:Xst:2588 - Port <a> of top entity <ALU> is not constrainted.
ERROR:Xst:2588 - Port <b> of top entity <ALU> is not constrainted.
ERROR:Xst:2588 - Port <op> of top entity <ALU> is not constrainted.
ERROR:Xst:2588 - Port <y> of top entity <ALU> is not constrainted.

Any help please?
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity ALU is
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    Port ( a : in  STD_LOGIC_VECTOR;
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           b : in  STD_LOGIC_VECTOR;
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           c_in : in  STD_LOGIC;
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           op : in  STD_LOGIC_VECTOR;
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           y : out  STD_LOGIC_VECTOR;
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           c_out : out  STD_LOGIC;
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           v : out  STD_LOGIC;
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           z : out  STD_LOGIC;
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           s : out  STD_LOGIC );
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end ALU;
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architecture Behavioral of ALU is
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  signal signal_a : STD_LOGIC_VECTOR (7 downto 0);
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  signal signal_b : STD_LOGIC_VECTOR (7 downto 0);
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  signal signal_c_in :STD_LOGIC;
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  signal signal_output : STD_LOGIC_VECTOR (7 downto 0);
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  signal signal_c_out : STD_LOGIC;
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  signal unsigned_a, unsigned_b : unsigned (7 downto 0);
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  signal unsigned_c_in : unsigned (0 downto 0);
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  signal unsigned_output : unsigned (8 downto 0);
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  signal not_a : STD_LOGIC_VECTOR (7 downto 0);
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  signal a_and_b : STD_LOGIC_VECTOR (7 downto 0);
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  signal a_or_b : STD_LOGIC_VECTOR (7 downto 0);
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  signal a_xor_b : STD_LOGIC_VECTOR (7 downto 0);
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  signal signal_y : STD_LOGIC_VECTOR (7 downto 0);
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begin
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  signal_a <= NOT(a) when op = "0110"
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          else a;
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  signal_b <= NOT(b) when op = "1111"
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          else "11111111" when op = "1110"
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          else "00000000" when op = "0111" OR op = "0001"
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          else b;
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  signal_c_in <= '1' when op = "1111" OR op = "0001" OR op = "0110"
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            else '0' when op = "1000"
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            else c_in;
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  not_a <= NOT(a);
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  a_or_b <= a OR b;
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  a_and_b <= a AND b;
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  a_xor_b <= a XOR b;
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  signal_y <= signal_output when op = "0000" else -- ADD
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          signal_output when op = "1111" else -- SUB
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          signal_output when op = "0110" else -- NEG
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          signal_output when op = "0001" else -- INC
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          signal_output when op = "1110" else -- DEC
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          not_a when op = "0101" else
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          a_or_b when op = "0111" else
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          a_and_b when op = "0110" else
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          a_xor_b when op = "1000" else
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          "--------";
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  unsigned_a <= unsigned(signal_a);
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  unsigned_b <= unsigned(signal_b);
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  unsigned_c_in(0) <= signal_c_in;
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  unsigned_output <= ("0" & unsigned_a) + unsigned_b + unsigned_c_in;
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  signal_output <= std_logic_vector(unsigned_output(7 downto 0));
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  signal_c_out <= unsigned_output(8);
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  y <= signal_y;
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  v <=  ((signal_a(7) AND signal_b(7) AND NOT signal_output(7)) 
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      OR (NOT signal_a(7)AND NOT signal_b(7) AND signal_output(7))) 
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      when op = "0000" OR op = "1111" OR op = "0110" OR op = "0001" OR op = "1110"
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      else '0';
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  z <=   '1' when signal_y = "00000000"
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      else '0';
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  s <=   signal_y(7);
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  c_out <= signal_c_out when op = "0000" OR op = "1111" OR op = "0110" OR op = "0001" OR op = "1110"
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        else '0';
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end Behavioral;

von Bitflüsterer (Guest)


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You forgot to declare the width of the vectors.

BTW: c_out seems to be a vector too.

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