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Forum: FPGA, VHDL & Verilog A VHDL Counter


von Resha L. (Company: Resige) (tahmod)


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I want to understand this code. Can anyone tell help me, how does it 
work?
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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use ieee.std_logic_arith.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity leds2_8 is
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GENERIC (n:positive := 2**22);
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    Port ( clkin : in  STD_LOGIC;
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           clkout : out  STD_LOGIC;
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           leds : out  STD_LOGIC_VECTOR (7 downto 0));
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end leds2_8;
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architecture Behavioral of leds2_8 is 
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begin
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PROCESS (clkin)
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VARIABLE count: INTEGER RANGE 0 to n;
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variable counter : integer range 0 to 255;
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BEGIN
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IF(clkin'EVENT AND clkin='1') THEN
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count :=count + 1;
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IF(count=n/2) THEN
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clkout <='1';
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ELSIF (count=n) THEN
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clkout <='0';
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count :=0;
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counter :=counter+1;
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leds <=conv_std_logic_vector(counter,8);
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END IF;
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END IF;
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END PROCESS;
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end  Behavioral;

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


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This code is ugly and bad formatted.


But have a look at my comments:
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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--use ieee.std_logic_arith.all;     -- it is a stupid idea to include both arithmetic libraries!
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entity leds2_8 is
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  GENERIC (n:positive := 2**22);    -- define n as a very big number
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    Port ( clkin : in  STD_LOGIC;   -- clkin i the oscillator input
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           clkout : out  STD_LOGIC; -- read my comments to this signal down a few lines
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           leds : out  STD_LOGIC_VECTOR (7 downto 0)); -- the led pins
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end leds2_8;
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architecture Behavioral of leds2_8 is 
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begin
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  PROCESS (clkin)      -- this process is sensitive to the clkin signal
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  VARIABLE count: INTEGER RANGE 0 to n := 0;      -- why the heck does everybody use variables nowadays?
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  variable counter : integer range 0 to 255 := 0; -- at least the variables MUST be initialized!
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                                                  -- otherwise the simulation will not work!
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  BEGIN
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    IF(clkin'EVENT AND clkin='1') THEN  -- you could use the rising_edge() insted
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      count :=count + 1;                -- count up the prescaler every clock
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      IF(count=n/2) THEN                -- here comes a way to get fired immediately: if you present me a clock
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        clkout <='1';                   -- generated this way you will work somewhere else next day!
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                                        -- clocks are generated with clock managers on a FPGA!
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      ELSIF (count=n) THEN              -- ok, lets go on. here the prescaler reaches its end value
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        clkout <='0';                   
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        count :=0;                      -- reset the prescaler-counter
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        counter :=counter+1;            -- and increment the led-counter
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        leds <=conv_std_logic_vector(counter,8); -- transfer the led counter to the leds
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      END IF;
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    END IF;
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  END PROCESS;
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end  Behavioral;

: Edited by Moderator

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