A VHDL Counter

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.numeric_std.all;

--use ieee.std_logic_arith.all;     -- it is a stupid idea to include both arithmetic libraries!

entity leds2_8 is

  GENERIC (n:positive := 2**22);    -- define n as a very big number

    Port ( clkin : in  STD_LOGIC;   -- clkin i the oscillator input

           clkout : out  STD_LOGIC; -- read my comments to this signal down a few lines

           leds : out  STD_LOGIC_VECTOR (7 downto 0)); -- the led pins

end leds2_8;

architecture Behavioral of leds2_8 is 

begin

  PROCESS (clkin)      -- this process is sensitive to the clkin signal

  VARIABLE count: INTEGER RANGE 0 to n := 0;      -- why the heck does everybody use variables nowadays?

  variable counter : integer range 0 to 255 := 0; -- at least the variables MUST be initialized!

                                                  -- otherwise the simulation will not work!

  BEGIN

    IF(clkin'EVENT AND clkin='1') THEN  -- you could use the rising_edge() insted

      count :=count + 1;                -- count up the prescaler every clock

      IF(count=n/2) THEN                -- here comes a way to get fired immediately: if you present me a clock

        clkout <='1';                   -- generated this way you will work somewhere else next day!

                                        -- clocks are generated with clock managers on a FPGA!

      ELSIF (count=n) THEN              -- ok, lets go on. here the prescaler reaches its end value

        clkout <='0';                   

        count :=0;                      -- reset the prescaler-counter

        counter :=counter+1;            -- and increment the led-counter

        leds <=conv_std_logic_vector(counter,8); -- transfer the led counter to the leds

      END IF;

    END IF;

  END PROCESS;

end  Behavioral;