I want to understand this code. Can anyone tell help me, how does it
work?
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use ieee.numeric_std.all;
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4 | use ieee.std_logic_arith.all;
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5 |
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6 |
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7 | -- Uncomment the following library declaration if using
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8 | -- arithmetic functions with Signed or Unsigned values
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9 | --use IEEE.NUMERIC_STD.ALL;
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10 |
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11 | -- Uncomment the following library declaration if instantiating
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12 | -- any Xilinx primitives in this code.
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13 | --library UNISIM;
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14 | --use UNISIM.VComponents.all;
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15 |
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16 | entity leds2_8 is
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17 | GENERIC (n:positive := 2**22);
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18 | Port ( clkin : in STD_LOGIC;
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19 | clkout : out STD_LOGIC;
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20 | leds : out STD_LOGIC_VECTOR (7 downto 0));
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21 | end leds2_8;
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22 |
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23 | architecture Behavioral of leds2_8 is
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24 | begin
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25 | PROCESS (clkin)
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26 | VARIABLE count: INTEGER RANGE 0 to n;
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27 | variable counter : integer range 0 to 255;
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28 |
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29 | BEGIN
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30 | IF(clkin'EVENT AND clkin='1') THEN
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31 | count :=count + 1;
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32 | IF(count=n/2) THEN
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33 | clkout <='1';
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34 | ELSIF (count=n) THEN
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35 | clkout <='0';
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36 |
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37 | count :=0;
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38 | counter :=counter+1;
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39 | leds <=conv_std_logic_vector(counter,8);
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40 | END IF;
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41 | END IF;
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42 | END PROCESS;
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43 | end Behavioral;
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