entity auf1 is port ( i : in std_logic_vector(0 to 2); d : out std_logic ); end entity auf1; architecture one of auf1 is variable a : std_logic := 'U'; variable b : std_logic := 'U'; variable c : std_logic := 'U'; begin a <= i(0); b <= i(1); c <= i(2); d <= (not a and b and c); end architecture; _______________________________________ I wanted in these Code make some variables out of an array (1.2.3.Entry). How do I correct make the assignment? The Input is the array i, the output the logic value d.
If you are a beginner with vhdl use signal instead of variable. Duke
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