regarding for loop in counter of verilog

Hi
i want a verilog code for a counter which should count 16 clock pulses 
so that the load should become zero when it start counting and should 
become high when completion of 16 clock pulses,remain high for a next 
pulse and again should become low when the counter starts counting with 
respect to reset.Finally this should happen for 8 times
plz help me out as soon as possible.