EmbDev.net

Forum: FPGA, VHDL & Verilog regarding for loop in counter of verilog


regarding for loop in counter of verilog
von Sarvani N. (sarvani)

Rate this post
0 ▲ useful
▼ not useful 
Hi
i want a verilog code for a counter which should count 16 clock pulses 
so that the load should become zero when it start counting and should 
become high when completion of 16 clock pulses,remain high for a next 
pulse and again should become low when the counter starts counting with 
respect to reset.Finally this should happen for 8 times
plz help me out as soon as possible.

Report post Edit Move Thread sperren Anmeldepflicht aktivieren Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Re: regarding for loop in counter of verilog
von PittyJ (Guest)

Rate this post
0 ▲ useful
▼ not useful 
Why do you want such a code?
Why do you not code it yourself?

Report post Edit Delete Quote selected text Reply Reply with quote
Re: regarding for loop in counter of verilog
von Sarvani N. (sarvani)

Rate this post
0 ▲ useful
▼ not useful 
i need it for my project
i can't make it out plzz help me out

Report post Edit Delete Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]



Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.