Hi everybody,
I want to create a testbench for a vhdl-ams code but I can't fix the
errors in compilation.
Below, I show you how I usually write a component and his correspondant
testbench in vhdl:
CODE:
1 | library IEEE;
|
2 | use IEEE.std_logic_1164.all;
|
3 | use IEEE.std_logic_unsigned.all;
|
4 |
|
5 | entity compteur is
|
6 |
|
7 | generic (N : integer:= 8);
|
8 |
|
9 | port(clk : in std_logic;
|
10 | reset: in std_logic;
|
11 | load : in std_logic;
|
12 | data : in std_logic_vector (N-1 downto 0);
|
13 | flag : out bit;
|
14 | Q : out std_logic_vector (N-1 downto 0));
|
15 |
|
16 | end compteur;
|
17 |
|
18 | architecture archi of compteur is
|
19 |
|
20 | signal Qtmp: std_logic_vector (N-1 downto 0);
|
21 | constant value : std_logic_vector := "00000111";
|
22 |
|
23 | begin
|
24 |
|
25 | process (clk, reset)
|
26 |
|
27 |
|
28 |
|
29 | begin
|
30 | if clk 'event and clk = '1' then
|
31 | if reset = '0' then
|
32 | Qtmp <= (others => '0');
|
33 |
|
34 | elsif load ='1' then Qtmp <= data;
|
35 |
|
36 | else Qtmp <= Qtmp + 1;
|
37 |
|
38 | end if;
|
39 |
|
40 | end if;
|
41 |
|
42 | end process;
|
43 |
|
44 | Q <= Qtmp;
|
45 | flag <= '1' when Qtmp = value else '0';
|
46 |
|
47 | end archi;
|
TESTBENCH:
1 | Library IEEE;
|
2 | Use IEEE.std_logic_1164.all;
|
3 | library work;
|
4 | use work.all;
|
5 |
|
6 | entity compteur_tb is
|
7 | end compteur_tb;
|
8 |
|
9 | architecture archi of compteur_tb is
|
10 |
|
11 | component compteur
|
12 |
|
13 | generic (N : integer:= 8);
|
14 |
|
15 | port(clk : in std_logic;
|
16 | reset: in std_logic;
|
17 | load : in std_logic;
|
18 | data : in std_logic_vector (N-1 downto 0);
|
19 | flag : out bit;
|
20 | Q : out std_logic_vector (N-1 downto 0));
|
21 |
|
22 | end component;
|
23 |
|
24 | signal clk : std_logic;
|
25 | signal reset: std_logic;
|
26 | signal load : std_logic;
|
27 | signal data : std_logic_vector (7 downto 0);
|
28 | signal flag : bit;
|
29 | signal Q : std_logic_vector (7 downto 0);
|
30 |
|
31 | constant T : time := 50 ns;
|
32 |
|
33 | begin
|
34 | uut: compteur port map (clk => clk, reset => reset, load => load, data => data, flag => flag, Q => Q);
|
35 |
|
36 | clk_proc: process
|
37 | begin
|
38 |
|
39 | loop
|
40 | clk <= '0';
|
41 | wait for T/2;
|
42 | clk <= '1';
|
43 | wait for T/2;
|
44 | end loop;
|
45 | end process clk_proc;
|
46 |
|
47 |
|
48 | stimuli: process
|
49 | begin
|
50 |
|
51 | reset <= '0';
|
52 | load <= '1';
|
53 | data <= "00000011";
|
54 | wait for 40 ns;
|
55 | reset <= '1';
|
56 | load <= '1';
|
57 | wait for 100 ns;
|
58 | reset <= '1';
|
59 | load <= '0';
|
60 | wait for 200 ns;
|
61 | reset <= '1';
|
62 | load <= '0';
|
63 | wait for 100 ns;
|
64 | reset <= '1';
|
65 | load <= '0';
|
66 | wait for 200 ns;
|
67 | reset <= '0';
|
68 | load <= '0';
|
69 | wait for 150 ns;
|
70 |
|
71 | assert false report "NONE. End of simulation." severity
|
72 | failure;
|
73 | wait for 100 us;
|
74 |
|
75 |
|
76 | end process stimuli;
|
77 |
|
78 | end archi;
|
Now in vhdl-ams:
1 | library ieee;
|
2 | use ieee.electrical_systems.all;
|
3 | use ieee.std_logic_1164.all;
|
4 | use ieee.math_real.all;
|
5 |
|
6 | entity comparateur is
|
7 |
|
8 | generic (level : real := 2.5; -- seuil
|
9 | vcc : real := 5.0; -- etat haut sortie
|
10 | gnd : real := 0.0); -- etat bas sortie
|
11 |
|
12 | port(terminal e: electrical; -- entree analogique
|
13 | signal s: out real); -- sortie numerique
|
14 |
|
15 | end comparateur;
|
16 |
|
17 | architecture archi of comparateur is
|
18 |
|
19 | quantity v across e; -- across quantity to ground
|
20 |
|
21 | begin
|
22 |
|
23 | s <= vcc when v'Above(level) -- v > level
|
24 | else gnd; -- v < level
|
25 |
|
26 | end archi;
|
1 | library ieee;
|
2 | use ieee.electrical_systems.all;
|
3 | use ieee.std_logic_1164.all;
|
4 | use ieee.math_real.all;
|
5 | library st_lib;
|
6 | use st_lib.all;
|
7 |
|
8 | entity comparateur_tb is
|
9 | end entity comparateur_tb;
|
10 |
|
11 | architecture archi of comparateur_tb is
|
12 |
|
13 | component comparateur
|
14 |
|
15 | generic (level : real := 2.5; -- seuil
|
16 | vcc : real := 5.0; -- etat haut sortie
|
17 | gnd : real := 0.0); -- etat bas sortie
|
18 |
|
19 | port(terminal e: electrical;
|
20 | signal s: out real);
|
21 |
|
22 | end component;
|
23 |
|
24 | signal e : electrical;
|
25 | signal s: real;
|
26 |
|
27 | constant T : time := 10 ns;
|
28 |
|
29 | begin
|
30 |
|
31 | uut: comparateur port map (e => e, s => s);
|
32 |
|
33 | stimuli: process
|
34 | begin
|
35 |
|
36 | loop
|
37 | e <= 5.0;
|
38 | wait for T/2;
|
39 | e <= 0.0;
|
40 | wait for T/2;
|
41 |
|
42 | end loop;
|
43 |
|
44 | assert false report "NONE. End of simulation." severity
|
45 | failure;
|
46 | wait for 100 us;
|
47 |
|
48 | end process stimuli;
|
49 |
|
50 | end archi;
|
And when I compile testbench I'm getting these errors:
ncvhdl -work st_lib -ams -message ../sources/comparateur_ent.
vhdl ../sources/comparateur_arch.vhdl ../sources/comparateur_tb.vhdl
ncvhdl: 13.10-s013: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
../sources/comparateur_ent.vhdl:
errors: 0, warnings: 0
../sources/comparateur_arch.vhdl:
errors: 0, warnings: 0
../sources/comparateur_tb.vhdl:
signal e : electrical;
|
ncvhdl_p: *E,EXPTYM (../sources/comparateur_tb.vhdl,24|20): type mark
expected [
4.2].
uut: comparateur port map (e => e, s => s);
|
ncvhdl_p: *E,IDENTU (../sources/comparateur_tb.vhdl,31|33): identifier
(E) is no
t declared [10.3].
e <= 5.0;
|
ncvhdl_p: *E,IDENTU (../sources/comparateur_tb.vhdl,37|3): identifier
(E) is not
declared [10.3].
e <= 0.0;
|
ncvhdl_p: *E,IDENTU (../sources/comparateur_tb.vhdl,39|4): identifier
(E) is not
declared [10.3].
errors: 4, warnings: 0
Do you know why and how to fix it ?
Even if this is no comparaison between compteur (counter) and
comparateur (comparator), I show you that to see how I do usually.
Thanks in advance!
Watch this topic
Disable multi-page view