Hi everybody,
I want to create a testbench for a vhdl-ams code but I can't fix the
errors in compilation.
Below, I show you how I usually write a component and his correspondant
testbench in vhdl:
CODE:
1 | library IEEE;
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2 | use IEEE.std_logic_1164.all;
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3 | use IEEE.std_logic_unsigned.all;
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4 |
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5 | entity compteur is
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6 |
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7 | generic (N : integer:= 8);
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8 |
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9 | port(clk : in std_logic;
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10 | reset: in std_logic;
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11 | load : in std_logic;
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12 | data : in std_logic_vector (N-1 downto 0);
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13 | flag : out bit;
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14 | Q : out std_logic_vector (N-1 downto 0));
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15 |
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16 | end compteur;
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17 |
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18 | architecture archi of compteur is
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19 |
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20 | signal Qtmp: std_logic_vector (N-1 downto 0);
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21 | constant value : std_logic_vector := "00000111";
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22 |
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23 | begin
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24 |
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25 | process (clk, reset)
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26 |
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27 |
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28 |
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29 | begin
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30 | if clk 'event and clk = '1' then
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31 | if reset = '0' then
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32 | Qtmp <= (others => '0');
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33 |
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34 | elsif load ='1' then Qtmp <= data;
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35 |
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36 | else Qtmp <= Qtmp + 1;
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37 |
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38 | end if;
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39 |
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40 | end if;
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41 |
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42 | end process;
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43 |
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44 | Q <= Qtmp;
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45 | flag <= '1' when Qtmp = value else '0';
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46 |
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47 | end archi;
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TESTBENCH:
1 | Library IEEE;
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2 | Use IEEE.std_logic_1164.all;
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3 | library work;
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4 | use work.all;
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5 |
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6 | entity compteur_tb is
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7 | end compteur_tb;
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8 |
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9 | architecture archi of compteur_tb is
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10 |
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11 | component compteur
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12 |
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13 | generic (N : integer:= 8);
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14 |
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15 | port(clk : in std_logic;
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16 | reset: in std_logic;
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17 | load : in std_logic;
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18 | data : in std_logic_vector (N-1 downto 0);
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19 | flag : out bit;
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20 | Q : out std_logic_vector (N-1 downto 0));
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21 |
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22 | end component;
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23 |
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24 | signal clk : std_logic;
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25 | signal reset: std_logic;
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26 | signal load : std_logic;
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27 | signal data : std_logic_vector (7 downto 0);
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28 | signal flag : bit;
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29 | signal Q : std_logic_vector (7 downto 0);
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30 |
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31 | constant T : time := 50 ns;
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32 |
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33 | begin
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34 | uut: compteur port map (clk => clk, reset => reset, load => load, data => data, flag => flag, Q => Q);
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35 |
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36 | clk_proc: process
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37 | begin
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38 |
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39 | loop
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40 | clk <= '0';
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41 | wait for T/2;
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42 | clk <= '1';
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43 | wait for T/2;
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44 | end loop;
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45 | end process clk_proc;
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46 |
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47 |
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48 | stimuli: process
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49 | begin
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50 |
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51 | reset <= '0';
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52 | load <= '1';
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53 | data <= "00000011";
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54 | wait for 40 ns;
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55 | reset <= '1';
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56 | load <= '1';
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57 | wait for 100 ns;
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58 | reset <= '1';
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59 | load <= '0';
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60 | wait for 200 ns;
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61 | reset <= '1';
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62 | load <= '0';
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63 | wait for 100 ns;
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64 | reset <= '1';
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65 | load <= '0';
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66 | wait for 200 ns;
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67 | reset <= '0';
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68 | load <= '0';
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69 | wait for 150 ns;
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70 |
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71 | assert false report "NONE. End of simulation." severity
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72 | failure;
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73 | wait for 100 us;
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74 |
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75 |
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76 | end process stimuli;
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77 |
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78 | end archi;
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Now in vhdl-ams:
1 | library ieee;
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2 | use ieee.electrical_systems.all;
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3 | use ieee.std_logic_1164.all;
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4 | use ieee.math_real.all;
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5 |
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6 | entity comparateur is
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7 |
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8 | generic (level : real := 2.5; -- seuil
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9 | vcc : real := 5.0; -- etat haut sortie
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10 | gnd : real := 0.0); -- etat bas sortie
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11 |
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12 | port(terminal e: electrical; -- entree analogique
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13 | signal s: out real); -- sortie numerique
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14 |
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15 | end comparateur;
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16 |
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17 | architecture archi of comparateur is
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18 |
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19 | quantity v across e; -- across quantity to ground
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20 |
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21 | begin
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22 |
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23 | s <= vcc when v'Above(level) -- v > level
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24 | else gnd; -- v < level
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25 |
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26 | end archi;
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1 | library ieee;
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2 | use ieee.electrical_systems.all;
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3 | use ieee.std_logic_1164.all;
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4 | use ieee.math_real.all;
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5 | library st_lib;
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6 | use st_lib.all;
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7 |
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8 | entity comparateur_tb is
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9 | end entity comparateur_tb;
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10 |
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11 | architecture archi of comparateur_tb is
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12 |
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13 | component comparateur
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14 |
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15 | generic (level : real := 2.5; -- seuil
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16 | vcc : real := 5.0; -- etat haut sortie
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17 | gnd : real := 0.0); -- etat bas sortie
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18 |
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19 | port(terminal e: electrical;
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20 | signal s: out real);
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21 |
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22 | end component;
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23 |
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24 | signal e : electrical;
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25 | signal s: real;
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26 |
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27 | constant T : time := 10 ns;
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28 |
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29 | begin
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30 |
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31 | uut: comparateur port map (e => e, s => s);
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32 |
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33 | stimuli: process
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34 | begin
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35 |
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36 | loop
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37 | e <= 5.0;
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38 | wait for T/2;
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39 | e <= 0.0;
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40 | wait for T/2;
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41 |
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42 | end loop;
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43 |
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44 | assert false report "NONE. End of simulation." severity
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45 | failure;
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46 | wait for 100 us;
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47 |
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48 | end process stimuli;
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49 |
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50 | end archi;
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And when I compile testbench I'm getting these errors:
ncvhdl -work st_lib -ams -message ../sources/comparateur_ent.
vhdl ../sources/comparateur_arch.vhdl ../sources/comparateur_tb.vhdl
ncvhdl: 13.10-s013: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
../sources/comparateur_ent.vhdl:
errors: 0, warnings: 0
../sources/comparateur_arch.vhdl:
errors: 0, warnings: 0
../sources/comparateur_tb.vhdl:
signal e : electrical;
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ncvhdl_p: *E,EXPTYM (../sources/comparateur_tb.vhdl,24|20): type mark
expected [
4.2].
uut: comparateur port map (e => e, s => s);
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ncvhdl_p: *E,IDENTU (../sources/comparateur_tb.vhdl,31|33): identifier
(E) is no
t declared [10.3].
e <= 5.0;
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ncvhdl_p: *E,IDENTU (../sources/comparateur_tb.vhdl,37|3): identifier
(E) is not
declared [10.3].
e <= 0.0;
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ncvhdl_p: *E,IDENTU (../sources/comparateur_tb.vhdl,39|4): identifier
(E) is not
declared [10.3].
errors: 4, warnings: 0
Do you know why and how to fix it ?
Even if this is no comparaison between compteur (counter) and
comparateur (comparator), I show you that to see how I do usually.
Thanks in advance!