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Forum: FPGA, VHDL & Verilog testbench in vhdl-ams


von sebgimi (Guest)


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Hi everybody,

I want to create a testbench for a vhdl-ams code but I can't fix the 
errors in compilation.

Below, I show you how I usually write a component and his correspondant 
testbench in vhdl:

CODE:
1
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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5
entity compteur is
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  generic (N : integer:= 8);
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  port(clk  : in std_logic;
10
       reset: in std_logic;
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       load : in std_logic;
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       data : in std_logic_vector (N-1 downto 0);
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       flag : out bit;
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       Q    : out std_logic_vector (N-1 downto 0));
15
       
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end compteur;
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architecture archi of compteur is
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signal Qtmp: std_logic_vector (N-1 downto 0);
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constant value : std_logic_vector := "00000111";
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begin
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  process (clk, reset)
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27
  
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  begin
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    if clk 'event and clk = '1' then
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      if reset = '0' then
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        Qtmp <= (others => '0');
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      elsif load ='1' then Qtmp <= data;
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      else Qtmp <= Qtmp + 1;
37
        
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      end if;
39
    
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    end if;
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  end process;
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Q <= Qtmp;
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flag <= '1' when Qtmp = value else '0';
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end archi;

TESTBENCH:
1
Library IEEE;
2
Use IEEE.std_logic_1164.all;
3
library work;
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use work.all;
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entity compteur_tb is
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end compteur_tb;
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architecture archi of compteur_tb is
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component compteur
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  generic (N : integer:= 8);
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  port(clk  : in std_logic;
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       reset: in std_logic;
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       load : in std_logic;
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            data : in std_logic_vector (N-1 downto 0);
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       flag : out bit;
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       Q    : out std_logic_vector (N-1 downto 0));
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end component;
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signal clk  : std_logic;
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signal reset: std_logic;
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signal load : std_logic;
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signal data : std_logic_vector (7 downto 0);
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signal flag : bit;
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signal Q    : std_logic_vector (7 downto 0);
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constant T : time := 50 ns;
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begin
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  uut: compteur port map (clk => clk, reset => reset, load => load, data => data, flag => flag, Q => Q);
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  clk_proc: process
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  begin
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    loop
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      clk <= '0';
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       wait for T/2;
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       clk <= '1';
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       wait for T/2;
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    end loop;
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  end process clk_proc;
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  stimuli: process
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  begin
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    reset <= '0';
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    load <= '1';
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    data <= "00000011";
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    wait for 40 ns;
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    reset <= '1';
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    load <= '1';
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    wait for 100 ns;
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    reset <= '1';
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    load <= '0';
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    wait for 200 ns;
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    reset <= '1';
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    load <= '0';
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    wait for 100 ns;
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    reset <= '1';
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    load <= '0';
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    wait for 200 ns;    
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    reset <= '0';
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    load <= '0';
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    wait for 150 ns;
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    assert false report "NONE. End of simulation." severity
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    failure;
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    wait for 100 us;
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  end process stimuli;
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end archi;

Now in vhdl-ams:
1
library ieee;
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use ieee.electrical_systems.all;
3
use ieee.std_logic_1164.all;
4
use ieee.math_real.all;
5
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entity comparateur is 
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  generic (level : real := 2.5;   -- seuil
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     vcc   : real := 5.0;   -- etat haut sortie
10
     gnd   : real := 0.0);  -- etat bas sortie
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  port(terminal e: electrical;  -- entree analogique
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             signal   s: out real); -- sortie numerique
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end comparateur;
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architecture archi of comparateur is 
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quantity v across e;       -- across quantity to ground
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begin 
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     s <= vcc when v'Above(level) -- v > level 
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     else gnd;                    -- v < level
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end archi;
1
library ieee;
2
use ieee.electrical_systems.all;
3
use ieee.std_logic_1164.all;
4
use ieee.math_real.all;
5
library st_lib;
6
use st_lib.all;
7
8
entity comparateur_tb is
9
end entity comparateur_tb;
10
11
architecture archi of comparateur_tb is
12
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component comparateur
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  generic (level : real := 2.5;   -- seuil
16
     vcc   : real := 5.0;   -- etat haut sortie
17
     gnd   : real := 0.0);  -- etat bas sortie
18
  
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  port(terminal e: electrical;
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       signal s: out real);
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end component;
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signal e : electrical;
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signal s: real;
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constant T : time := 10 ns;
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begin
30
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  uut: comparateur port map (e => e, s => s);
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  stimuli: process
34
  begin
35
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    loop
37
      e <= 5.0;
38
       wait for T/2;
39
       e <= 0.0;
40
       wait for T/2;
41
  
42
    end loop;
43
      
44
    assert false report "NONE. End of simulation." severity
45
    failure;
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    wait for 100 us;
47
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  end process stimuli;
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end archi;

And when I compile testbench I'm getting these errors:

ncvhdl -work st_lib -ams -message ../sources/comparateur_ent.
vhdl ../sources/comparateur_arch.vhdl ../sources/comparateur_tb.vhdl
ncvhdl: 13.10-s013: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
../sources/comparateur_ent.vhdl:
        errors: 0, warnings: 0
../sources/comparateur_arch.vhdl:
        errors: 0, warnings: 0
../sources/comparateur_tb.vhdl:
signal e : electrical;
                    |
ncvhdl_p: *E,EXPTYM (../sources/comparateur_tb.vhdl,24|20): type mark 
expected [
4.2].
        uut: comparateur port map (e => e, s => s);
                                        |
ncvhdl_p: *E,IDENTU (../sources/comparateur_tb.vhdl,31|33): identifier 
(E) is no
t declared [10.3].
                        e <= 5.0;
                        |
ncvhdl_p: *E,IDENTU (../sources/comparateur_tb.vhdl,37|3): identifier 
(E) is not
 declared [10.3].
                        e <= 0.0;
                        |
ncvhdl_p: *E,IDENTU (../sources/comparateur_tb.vhdl,39|4): identifier 
(E) is not
 declared [10.3].
        errors: 4, warnings: 0


Do you know why and how to fix it ?

Even if this is no comparaison between compteur (counter) and 
comparateur (comparator), I show you that to see how I do usually.

Thanks in advance!

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