Hi,
I'm beginner in VHDL,
I have to devide the frequency from 125 Mhz to 1 Hz
for that I used this code to generate the 1s clock
--- generate the 1s clock ---
process(clk,rst)
begin
if rst='1' then
cnt<=1;
else
cnt<=cnt+1;
end if;
if cnt<=62000000 then
clk_s<='0';
else
clk_s<='1';
end if;
if cnt=125000000 then
cnt<=1;
end if;
end process;
--------------------------------------------------------
the probleme is what's the value of clock (clk) I should define in
testbensh ( is it 8ns ??)
help me please! thank you.
Abdallah.
Guest
#3457439
Dont u have a calculator? The clockperiod is 1/(125*10e6 Hz)=8ns
thank you for your response guest!
I just confused because the simulation didn't provide the good result.
it provide clock of 0.5 second not 1 second.. where is the probleme!!!!
this is my code
---------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity one_second is
port(clk_in:in bit;
s:out bit);
end one_second;
architecture Behavioral of one_second is
signal cnt:integer:=1;
begin
process(clk_in)
begin
cnt<=cnt+1;
if cnt<=62500000 then
s<='0';
else
s<='1';
end if;
if cnt=125000000 then
cnt<=1;
end if;
end process;
end Behavioral;
--------------------------------------------------------
Guest
#3457894
There is no raising_edge.
Guest
#3457964
Try something like this: if rst = '1' then Cntr <= (others => '0'); Elsif clk = '1' and clk'event then Cntr <= cntr +1; --add your stuff; End if;
Guest
#3457995
> where is the probleme!!!! this is my code
One problem is, that the process is triggered with each change on
clk_in, so the counter counts at each rising and each falling edge of
clk_in.
But the much bigger problem is, that you do not know what you are doing!
Have a look how others write a counter and check your solution against
it.
BTW: your counter will work only in simulation. In real hardware it is a
combinational loop...
That's true about the counter, I change its value to 125E06 for each front. it's work only when I decreases the counter to 125E03 with decreases of clock to 8us, or counter <= 125 with clock of 8ms.............. biiiiiiiiiiiig probleme when counter<=125000000 and clock=8ns....... the result is more than anarchy..(because of the computer!!!) what if I implement it to the board,does it work!!! --- what's your opinion? thany you.
Attached files:
-
anarchy.jpg
(190 KB)
------------------------------------------------------------------------
---
By the way M.lkmiller I really know what I do although that I'm still
beginner
....any way Thank you very much
------------------------------------------------------------------------
---
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity one_second is
port(clk_in:in bit;
s:out bit);
end one_second;
architecture Behavioral of one_second is
signal cnt:integer:=1;
begin
process(clk_in)
begin
cnt<=cnt+1;
if cnt<125000000 then
s<='0';
else
s<='1';
end if;
if cnt=250000000 then
cnt<=1;
end if;
end process;
end Behavioral;
------------------------------------------------------------------------
-
Guest
#3458131
Think in hardware. What are counters synthesise to? Do u know FF that works with rising AND falling edge? No? Me too!
Okay it's done, thanks to ALLAH
-------------------------------
this is the finale code with the description in the attachment file
........................................................
I hope that you give your opinion about the code and why not correct my
false steps.. thanks a lot.
-------------------------------------------------------------
-| |------
-| Controle d'un feu de circulation en utilisant les Machines d'Etats
-| Control of the traffic light using machines States
-------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
------------------------------
--- Entity ---
------------------------------
entity feu_circulation is
port( clk,rst,tst,a: in bit;
r1,r2:out std_logic_vector(2 downto 0));
end feu_circulation;
--------------------------------
--- Architecture ---
--------------------------------
architecture feu_circulation of feu_circulation is
type etat is(R_V,R_O,V_R,O_R,O_O);
signal p_etat,s_etat:etat;
signal clk_etat,clk_s:bit:='0';
signal cnt,tmps:integer:=1;
begin
------------------------------------------------------------------------
--- Changement de l'Etat Presente vers l'Etat Suivante ---
------------------------------------------------------------------------
process(rst,clk_etat)
begin
if rst='1' then
p_etat<=R_V;
elsif(clk_etat'event and clk_etat='1') then
p_etat<=s_etat;
end if;
end process;
---------------------------------------------------------------------
---Definition de l'Etat Suivante et les valeurs des Signaux de Sortie
--- Changing Presente State to Next State
---------------------------------------------------------------------
process(p_etat,a,tst)
begin
case p_etat is
when R_V =>r1<="100"; r2<="010";
if a='0' then
s_etat<=R_O;
else
s_etat<=O_O;
end if;
if tst='0' then tmps<=30; else tmps<=1; end if;
when R_O =>r1<="100"; r2<="001";
if a='0' then
s_etat<=V_R;
else
s_etat<=O_O;
end if;
if tst='0' then tmps<=5; else tmps<=1; end if;
when V_R =>r1<="010"; r2<="100";
if a='0' then
s_etat<=O_R;
else
s_etat<=O_O;
end if;
if tst='0' then tmps<=45; else tmps<=1; end if;
when O_R =>r1<="001"; r2<="100";
if a='0' then
s_etat<=R_V;
else
s_etat<=O_O;
end if;
if tst='0' then tmps<=5; else tmps<=1; end if;
when O_O =>r1<="001"; r2<="001";
if a='0' then
s_etat<=R_V;
else
s_etat<=O_O;
end if;
tmps<=1;
end case;
end process;
--------------------------------------------------------------------
--- Génération de l'horloge de 1s de période (clk_s) à partir de
l'horloge de 8ns de période (clk)
-------------------------------------
--- Generation of the clock period of 1s (clk_s) from the clock
period of 8ns (clk) ---
--------------------------------------------------------------------
process(clk,rst)
begin
if rst='1' then
cnt<=1;
else
cnt<=cnt+1;
end if;
if cnt<125 then--- to use clock periode of 8ns, use cnt<125000000.
note: It doesn't work in ISE Simulation
clk_s<='0'; -- to use clock periode of 8us, use cnt<125000.
else -- to use clock periode of 8ms, use cnt<125.
clk_s<='1';
end if;
if cnt=250 then--- to use clock periode of 8ns, use cnt<250000000.
note: It doesn't work in ISE Simulation
cnt<=1; -- to use clock periode of 8us, use cnt<250000.
end if; -- to use clock periode of 8ms, use cnt<250.
end process;
------------------------------------------------------------------------
--- Géneration de l'horloge de sorite (clk_etat) d'une période qui
varie selon les 3 Modes ---
------------------------
--- Generation of the output clock (clk_etat) of a period which
varies from 3 Modes ---
------------------------------------------------------------------------
process(clk_s,rst,a,tst)
variable temps:integer;
variable ok:bit:='1';
begin
if tst='1' then
ok:='1';
end if;
if rst='1' then
ok:='1';
elsif a='0' then
if ok='1' then
temps:=tmps;
ok:='0';
clk_etat<='0';
end if;
if clk_s'event and clk_s='1' then
temps:=temps-1;
if temps=0 then
ok:='1';
clk_etat<='1';
end if;
end if;
end if;
if a='1' then
clk_etat<=clk_s;
ok:='1';
end if;
end process;
end feu_circulation;
------------------------------------------------------------------------
-
--------| ||||||||||| |||||||||||| |||| ||||
|------
--------| ||||||||||| |||||||||||| ||||| ||||
|------
--------| |||| |||| |||||| ||||
|------
--------| |||| |||| ||||||| ||||
|------
--------| |||||||| |||| ||||||||||||
|------
--------| |||||||| |||| ||||||||||||
|------
--------| |||| |||| |||| |||||||
|------
--------| |||| |||||||||||| |||| ||||||
|------
--------| |||| |||||||||||| |||| |||||
|------
------------------------------------------------------------------------
-
----- Abdallah ---- Abdallah ---- Abdallah ---- Abdallah ------
------------------------------------------------------------------------
-
Attached files:
-
img013.jpg
(320 KB)
Guest
#3458978
Ohh man... There are many good books out there. Try to get one. This code is terrible...