HI its my first time here. Iam somehow new to vhdl, using a BASYS2. here is my top module and my counter + decoder. The thing i need help with, is that i want to show on the display: A digit between 0-9 on the first anod. b on the second anod. i on the third anod. t on the fourth anod. and they have to show at the same time, thats why iam using a counter. but cant seem to get it working. please help. ######################################################################## library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Top is port( clk : in std_logic; reset : in std_logic; enable : in std_logic; input1 : in STD_LOGIC_VECTOR (3 downto 0); segment : out STD_LOGIC_VECTOR (7 downto 0); anoder : out STD_LOGIC_VECTOR (3 downto 0)); end Top; architecture Behavioral of Top is ------------------------------------------------------ component counter is port( clk : in std_logic; reset : in std_logic; enable : in std_logic; count : out std_logic_vector(1 downto 0)); end component; ------------------------------------------------------ component Decoder is Port ( input : in STD_LOGIC_VECTOR (1 downto 0); input1 : in STD_LOGIC_VECTOR (3 downto 0); segment : out STD_LOGIC_VECTOR (7 downto 0); anoder : out STD_LOGIC_VECTOR (3 downto 0)); end component; ------------------------------------------------------ signal s : STD_LOGIC_VECTOR (1 downto 0); begin Count : counter port map (clk => clk, reset => reset, enable => enable, count => s); Display : Decoder port map (segment => segment, anoder => anoder, input => s, input1 => input1); end Behavioral; ######################################################################## library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port( clk: in std_logic; reset: in std_logic; enable: in std_logic; count: out std_logic_vector(1 downto 0) ); end counter; architecture Behavioral of counter is signal pre_count: std_logic_vector(1 downto 0); begin process(clk, enable, reset) begin if reset = '1' then pre_count <= "00"; elsif (clk='1' and clk'event) then if enable = '1' then pre_count <= pre_count + "1"; end if; end if; end process; count <= pre_count; end Behavioral; ######################################################################## library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Decoder is Port ( input : in STD_LOGIC_VECTOR (1 downto 0); input1 : in STD_LOGIC_VECTOR (3 downto 0); segment : out STD_LOGIC_VECTOR (7 downto 0); anoder : out STD_LOGIC_VECTOR (3 downto 0)); end Decoder; architecture Behavioral of Decoder is begin segment <= "00000011" when input1 = "0000" else -- 0 "10011111" when input1 = "0001" else -- 1 "00100101" when input1 = "0010" else -- 2 "00001101" when input1 = "0011" else -- 3 "10011001" when input1 = "0100" else -- 4 "01001001" when input1 = "0101" else -- 5 "01000001" when input1 = "0110" else -- 6 "00011111" when input1 = "0111" else -- 7 "00000001" when input1 = "1000" else -- 8 "00011001" when input1 = "1001" else -- 9 "11000001" when input = "10" else -- b "11110011" when input = "01" else -- i "11100001" when input = "00"; -- t anoder <= "0111" when input = "11" else "1011" when input = "10" else "1101" when input = "01" else "1110" when input = "00"; end Behavioral; ########################################################################
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