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Forum: FPGA, VHDL & Verilog Tri state buffer


von vhdl n. (Company: none) (pranoy)


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library ieee;
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use ieee.std_logic_1164.all;
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entity tristate_buffer is 
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port (enable: in std_logic;
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d_in: in std_logic_vector ( 7 downto 0 ) ;
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d_out: out std_logic_vector (7 downto 0 )) ;
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end tristate_buffer;
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architecture behavioral of tristate_buffer is
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begin
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process (enable,d_in)
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begin
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if (enable = 1) then
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d_out <= d_in;
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else
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d_out <= (zzzzzzzz);
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end if;
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end process;
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end behavioral;

what is the error in this program?
i get the following errors when i compile it in modelsim

tri_state_buffer.vhd(14): near "?": syntax error
tri_state_buffer.vhd(17): near "?": syntax error

von Schlumpf (Guest)


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Vectors: "ZZZZZZ" and not `ZZZZZZ´
Single Signals: '1' and not `1´

von vhdl n. (Company: none) (pranoy)


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Thanks
1
library ieee;
2
use ieee.std_logic_1164.all;
3
4
5
entity tristate_buffer is 
6
port (enable: in std_logic;
7
d_in: in std_logic_vector ( 7 downto 0 ) ;
8
d_out: out std_logic_vector (7 downto 0 )) ;
9
end tristate_buffer;
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architecture behavioral of tristate_buffer is
12
begin
13
process (enable,d_in)
14
begin
15
if (enable = '1') then
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d_out <= d_in;
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else
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d_out <= ("zzzzzzzz");
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end if;
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end process;
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end behavioral;

now the program is like this.
but new errors are coming like

tri_state_buffer.vhd(19): String literal has a character 'z' not in the 
enumeration type ieee.std_logic_1164.std_logic.

tri_state_buffer.vhd(22): VHDL Compiler exiting

pls help

von vhdl n. (Company: none) (pranoy)


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THANKS

Got it.

The high impedence should be Z instead of z. :)

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