EmbDev.net

Forum: FPGA, VHDL & Verilog RAM read and write


von vhdl n. (Company: none) (pranoy)


Rate this post
1 useful
not useful
1
library ieee;
2
use ieee.std_logic_1164.all;
3
--use ieee.std_logic_arith.all;
4
use ieee.std_logic_unsigned.all;
5
entity SRAM is
6
generic(width:integer:=4;depth:integer:=32);
7
port(
8
Clock:in std_logic;
9
Enable:in std_logic;
10
Read:in std_logic;
11
Write:in std_logic;
12
Read_Addr:in std_logic_vector(4 downto 0);
13
Write_Addr: in std_logic_vector(4 downto 0);
14
Data_in: in std_logic_vector(3 downto 0);
15
Data_out: out std_logic_vector(3 downto 0));
16
end SRAM;
17
18
architecture behav of SRAM is
19
    type ram_type is array (0 to 31) of
20
    std_logic_vector(3 downto 0);
21
    signal tmp_ram:ram_type;
22
    begin
23
        process(clock,read)
24
            begin
25
                if(clock'event and clock='1') then
26
                    if enable='1' then
27
                        if read='1' then
28
                            data_out<=tmp_ram(conv_integer(read_addr));
29
                            else
30
                            data_out<=(data_out'range=>'Z');
31
                        end if;
32
                    end if;
33
                end if;
34
            end process;
35
            process(clock,write)
36
                begin
37
                    if(clock'event and clock='1') then
38
                        if enable='1' then
39
                            if write='1' then
40
                                tmp_ram(conv_integer(write_addr))<=data_in;
41
                            end if;
42
                        end if;
43
                    end if;
44
                end process;
45
            end behav;

I got this code for RAM online.

When i run it in MODELSIM the writing takes a complete clock cycle(if 
clock starts with a +ve edge) and
reading takes 1 and 1/2 clock cycles(if clock starts with a +ve edge).


could anyone explain why is it so?

and also pls give me a way to make the read and write cycle within a 
single clock cycle.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.