HI everybody, I have created a small fifo in VHDL and I want to check the fifo integrity with a sort of scoreboard. I'm aware the concept of scoreboard is not yet implemented in VHDL, but there has to be a way to achieve my goal. My ideea was to create a reference memory array that stores data at every write action , then compare the data in the memory with the data at the reference model for the same address. But I'm stuck in some odd errors. Maybe you have faced challenges like this . If you have any advice I would appreciate it. How can be compared the content of two arrays? Thanks , Boby