i am using xylinx v 13.1 and using this i have written an fsm to interact between processor and fifo for a FIFO generated using core generator. the problem which i am facing is that the data will write and den the write data count of fifo will also rise but this happens only after 3 write write cylces. because of this am not able to obtain the data which i have written when i am enabling the read signal of the fifo . the write data count which should remain constant is also decrementing when i am reading the data. but the data read is only the second data written at this case. the problem which i found was that fifo full which was high inititally is going low only after 2 write clocks and the fifo empty is going low only after 3 write clocks. when i noticed this problem i added another state to solve this issue but then when i enable read signal of fifo it is only reading the first data.can any one help me with a soulution?
i am using xylinx v 13.1 and using this i have written an fsm to interact between processor and fifo for a FIFO generated using core generator. the problem which i am facing is that the data will write and den the write data count of fifo will also rise but this happens only after 3 write write cylces. because of this am not able to obtain the data which i have written when i am enabling the read signal of the fifo . the write data count which should remain constant is also decrementing when i am reading the data. but the data read is only the second data written at this case. the problem which i found was that fifo full which was high inititally is going low only after 2 write clocks and the fifo empty is going low only after 3 write clocks. when i noticed this problem i added another state to solve this issue but then when i enable read signal of fifo it is only reading the first data.can any one help me with a soulution?
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#3396552
hm, fifo control is not a big thing, mostly counting sime numbers and gatin at the right points of time you seem to have difficulties with a time line issue caused by the latency most probably. did you write down the time line for your code? usually documenting this in detail prior start shows the issue before a false implementation is began from here it is difficult so guess, where there might be a problem, since we do not have a clear image what you already did and what you really intend