Forum: FPGA, VHDL & Verilog Reading Verilog Code

von Syed H. (gamingx)

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Hi guys,

I'm familiar with using FPGAs and with Verilog and VHDL so I'm able to 
do a fair bit with it. But I have difficulty when reading somebody 
else's code. For example, I have this large project which uses an FPGA 
and it already contains the code so I'm trying to figure out how the 
code actually works, but I'm not sure where to start with it. Any 
guidelines or tips would be appreciated!

von Duke Scarring (Guest)

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In such a case I start with generating a hierarchy diagram to get an 
The next step is to identify the dataflow.
Or vice versa :-)



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