Forum: FPGA, VHDL & Verilog Help with State Machines and Timers

von A VHDL S. (almelia)

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Hey everyone, hoping you guys could give me some tips on how to finish 
my last VHDL assignment for this semester.

We have to program a vending machine according to assignment 
specifications. Part of this is displaying the coin inserted into the 
machine for 4 seconds after it has been inserted. Alternatively, if the 
coin you inserted causes the total amount to exceed the price, the SSD's 
must display the change being returned.

I have a state machine with 4 states: reset, ready, processing, paid.

In the ready state, the machine accepts new coins. When a new coin is 
inserted it goes to the 'processing' state. This state sets an enable 
signal (process_en) that goes to another component that calculates how 
much has been paid, how much is remaining, and if there is any change.

What I am struggling to do is set up a timer that counts for 4 seconds 
(with a 100Mhz clock) ONCE when process_en goes high, before sending a 
signal back to the state machine (state_en) that allows it to either go 
back  to ready state, or on to the finished state.

Below is what I have now, which simulates what I want but won't 
synthesize (I understand why, I just don't know how else to implement 
it). I feel like I'm missing something obvious, so if anyone could give 
me an idea of what else might work I would greatly appreciate it.

counter : process (clk, timer_en) is
if timer_en <= '1' then
  if clk'event and clk = '1' then
    timer <= '1';
    timer_count <= timer_count + 1;
    --if timer_count <= "10111110101111000010000000" then
    if timer_count = "0000000000000000000000000100" then
      timer_count <= "00000000000000000000000000";
      timer <= '0';
    end if;
  end if;
end if;
end process;

Timer Controller:
timer_controller : process is
wait until process_en = '1';
  state_en <= '0';
  timer_en <= '1';
wait until timer = '0';
  timer_en <= '0';
  state_en <= '1';
end process;

von PittyJ (Guest)

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You can not use wait, if you want to synthesize it.
Use also a state machine in the timer_controller.


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