EmbDev.net

Forum: FPGA, VHDL & Verilog Deriving a clock from another clock


Deriving a clock from another clock
von Stuart (Guest)

Rate this post
• ▲ useful
▼ not useful 
Hi all

I am new to VHDL and I am in my learning phase .It will be nice if you 
can help me with this :


I want to derive a new_clock from  old_clock .

The old_clock has a clock period of 30ns.

One clock pulse of old_clock should generate 7 clock pulses of new clock 
(1 old_clock = 7 new_clock)


I am not getting a clear logic for this . Please help

Thanks in advance.

Report post Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Re: Deriving a clock from another clock
von Marius (Guest)

Rate this post
• ▲ useful
▼ not useful 
Take a PLL for this. This is not pure logic anymore.

Cheers, Marius

Report post Edit Delete Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view
Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
No account? Register here.