Deriving a clock from another clock

Hi all

I am new to VHDL and I am in my learning phase .It will be nice if you 
can help me with this :


I want to derive a new_clock from  old_clock .

The old_clock has a clock period of 30ns.

One clock pulse of old_clock should generate 7 clock pulses of new clock 
(1 old_clock = 7 new_clock)


I am not getting a clear logic for this . Please help

Thanks in advance.