1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | entity enc_ent is
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4 | port(enable:in std_logic;
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5 | d:in std_logic_vector(7 downto 0);
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6 | y:out std_logic_vector(2 downto 0)
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7 | );
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8 |
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9 | architecture enc_arc of enc_ent is
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10 | begin
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11 | process(enable,d)
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12 | begin
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13 | if(enable='1') then
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14 | case d is
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15 | when "00000001"=> y<="000";
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16 | when "00000010"=> y<="001";
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17 | when "00000100"=> y<="010";
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18 | when "00001000"=> y<="011";
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19 | when "00010000"=> y<="100";
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20 | when "00100000"=> y<="101";
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21 | when "01000000"=> y<="110";
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22 | when others=> y<="111";
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23 | end case;
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24 | else
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25 | y<="UUU";
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26 | end if;
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27 | end process;
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28 | end enc_arc;
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this is my code
but i get this error message.
encoder.vhd(9): near "architecture": expecting: END
can u tell what is the problem?