single and double precision matrix matrix multiply

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I need to use it for comparing FPGA's computational performance. I am 
using Xilinx Virtex 6-XC6VLX130T. I can generate floating point adders 
and multipliers via Xilinx Core generator. What I am interested in is 
the architecture design to maximize speed using maximum possible 
resources on the board (maximally parallel architecture). Any tutorial 
or any existing code on any architecture will be helpful.

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