Forum: FPGA, VHDL & Verilog vhdl file / package / entity

von entity / package (Guest)

Rate this post
0 useful
not useful
good morning how I can assemble a list of entities in a package ?
how I can point to another file vhdl ?

von Lothar M. (lkmiller) (Moderator)

Rate this post
0 useful
not useful
Why do you post the same question multiple times?

Pls describe your problem, not how you intend to solve it.
WHY do you want a list of entities in a package?
WHAT do you mean with a "pointer to a VHDL file"?


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.