Hallo All Hope every one is fine. I am trying to implement a communication master sysgtem on FPGA. I need some help in generating Ethernet Frame( VHDL code) or an open IP core which can handel ethernetMAC and IP . I would be realy greatfull if some one can help. FPGA i am working with is cyclone v SoC
You have Cyclone V SoC, what do you need ethernetMAC in VHDL for? You already have two of them inside of ARM-Core!
Is that right, one has hard built MACs in the ARMs? Did not know that
Ethernet is for testing and then i have to impelement PROFINET and my idea is to change ethernet frames to profinet frames and generate PROFINET traffic. Can you help me in generating EThernet traffice and how to creat an ethernet frame in vhdl and how i can transmit and recieve data? i am totaly new with fpga and dont have so good knowledge hope some one of you can help me Best Regards Abdullah Najam Raja