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Forum: FPGA, VHDL & Verilog clock skew problems after the implementation of ASIC


clock skew problems after the implementation of ASIC
Author: nelson g. (Company: student) (together)
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I have a basic doubt about clock skew.Consider during manufacturing time 
,I have optimized my design for minimum clock skew.Is there any chance 
for occurring the skew again in real time working of the ASIC?

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