Hello , Sincerly i'm newbie i'm not familiar with FPGA
I'm using the spartan6 and i have to communicate this fpaga with a DDR3
, so i used the MIG from COrgen , after that i'm using the example
design which i removed all files of Traffic generator and i remplaced it
by my onwn user interface which i use a state machie to read and Write
DATA ?
but my broblem now : firstly afetr generation of this part of project ,
how can i use it into my top project ( the other projet which i have
designed my work) if that is the case i'm asking if i'll add all the
source files palced in the rtl folder or not ?
- secondely i want to modify data written and readen into the memory ,
how can i use the procedure , i need simple example :(
- a little more question : i have to to use the data such as input
std_logic but this type INPUT it could be readen and written ?
- also someone can explain me how to modify and what is the difference
between these parmeters :
constant C3_CLKOUT0_DIVIDE : integer := 1;
constant C3_CLKOUT1_DIVIDE : integer := 1;
constant C3_CLKOUT2_DIVIDE : integer := 16;
constant C3_CLKOUT3_DIVIDE : integer := 8;
constant C3_CLKFBOUT_MULT : integer := 2;
constant C3_DIVCLK_DIVIDE : integer := 1;
Please any help