EmbDev.net

Forum: FPGA, VHDL & Verilog synthesis of a vhdl code


synthesis of a vhdl code
Author: siwar dammak (Company: ISIMSfax) (siwardammak)
Posted on:
Rate this post
0 ▲ useful
▼ not useful 
good morning
please how work synthesis of a vhdl code on modelSim to be configured in 
FPGA ?
thanks on advance

Report post Edit Move Thread sperren Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Re: synthesis of a vhdl code
Author: Lothar Miller (lkmiller) (Moderator)
Posted on:
Rate this post
0 ▲ useful
▼ not useful 
ModelSim is a simulator.
To synthesize a VHDL description you need a synthesizer. Thats usually 
included in the toolchain of the FPGA supplier...

Report post Edit Delete Quote selected text Reply Reply with quote
Re: synthesis of a vhdl code
Author: siwar dammak (Company: ISIMSfax) (siwardammak)
Posted on:
Rate this post
0 ▲ useful
▼ not useful 
thanks a lot

Report post Edit Delete Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]



Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.