synthesis of a vhdl code

siwar d. (siwardammak) OP (Company: ISIMSfax) 2013-06-06 17:12 #3193840

Rate this post

•	▲ useful ▼ not useful

good morning
please how work synthesis of a vhdl code on modelSim to be configured in 
FPGA ?
thanks on advance

Lothar M. (lkmiller) Moderator (Company: Titel) 2013-06-06 21:52 #3194145

Rate this post

•	▲ useful ▼ not useful

ModelSim is a simulator.
To synthesize a VHDL description you need a synthesizer. Thats usually 
included in the toolchain of the FPGA supplier...

siwar d. (siwardammak) OP (Company: ISIMSfax) 2013-06-06 22:21 #3194169

Rate this post

•	▲ useful ▼ not useful

thanks a lot

Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.

Text *

Formatting

[c]C-Code[/c]
[vhdl]VHDL-Code[/vhdl]
[code]code in other languages, ASCII drawings[/code]
[math]formula (LaTeX syntax)[/math]
[[Title]] – link to an article
Link to another post: right-click its post ID (#8078628), copy the address, paste it into the text

Attachments

Post long source code as an attachment, not in the text.

Your name and e-mail address

Already registered? Log in

First name *

Email address *

Not shown to anyone. We send you a link; your post appears once you confirm it there.

Watch this topic

By submitting you create a free account and accept the terms of use.