Verilog Input Syntax

Hi everyone,

Is it possible to define such inputs and outputs?

module Minimize(reg_inp, reg_out);

  input [3:0] reg_inp[0:255];
  output [3:0] reg_out[0:255];

  reg [3:0] reg_inp[0:255];
  reg [3:0] reg_out[0:255];

Thanks!