I need hel with the following verilog code . I must decrease the size of this circuit, only by repositioning the logic and the addSub modules. Can anyone help me ? module structuralAlu(output [31:0] out , output carryOut, input carryIn , input [31:0] left , right , input [2:0] func ); wire [31:0] shift, add_sub, arith, logic; mux2 shiftMux(.out(shift ), .in0(left ), .in1({1'b0, left[31:1]}), .sel(func[0] )), arithMux(.out(arith ), .in0(shift ), .in1(add_sub), .sel(func[1])), outMux(.out(out ), .in0(arith ), .in1(logic ), .sel(func[2])); logic log( .out (logic ), .left (left ), .right (right ), .op (func[1:0])); addSub addSub(.out (add_sub ), .cout (carryOut), .left (left ), .right (right ), .cin (carryIn ), .sub (func[0] )); endmodule module mux2(input sel , input [31:0] in0, in1, output [31:0] out ); assign out = sel ? in1 : in0; endmodule module addSub(output [31:0] out , output cout , input [31:0] left, right , input cin, sub ); assign {cout, out} = left + (right ^ {32{sub}}) + (cin ^ sub); endmodule module logic(output reg [31:0] out , input [31:0] left, right , input [1:0] op ); integer i; wire [3:0] f; assign f = {op[0], ~(~op[1] & op[0]), op[1], ~|op}; always @(left or right or f) for(i=0; i<32; i=i+1) logicSlice(out[i], left[i], right[i], f); task logicSlice; output o; input l, r; input [3:0] f; o = f[{l,r}]; endtask endmodule
you should provide a circuit diagram istead of the code to clarify the funcion you Need guessing the funcion from your Realisation is annoying
What size results the code above in? What size do you expect? Why is the design too big? What size is allowed?
This is the scheme on which the circuit is based. The design is not too big , but according to my teacher can be improved by repositioning those 2 block mentioned above. I wish to know how is that possible ?
>>> I must decrease the size of this circuit, only by repositioning >>> the logic and the addSub modules. > The design is not too big , but according to my teacher can be > improved by repositioning those 2 block mentioned above. Is "improved" the same as "decrease"? It seems to mee, that you should draw a new schematic with the same functionality, but with less ressources or less logic levels or higher speed...
Ok, first of all I would like to apologize for the error I have made. By "size" i meant "depth". My bad :(. Yes in this case "improved" means "decreased" ( we're talking about the circuit's depth ).I can't alter the code. The only way in which the depth must be reduced is to reposition those 2 modules.
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