Help in decreasing circuit size

I need hel with the following verilog code . I must decrease the size of 
this circuit, only by repositioning the logic and the addSub modules. 
Can anyone help me ?

module structuralAlu(output [31:0] out ,
                    output carryOut,
                    input carryIn ,
                    input [31:0] left , right ,
                    input [2:0] func );
                    wire [31:0] shift, add_sub, arith, logic;

mux2 shiftMux(.out(shift ),
             .in0(left ),
             .in1({1'b0, left[31:1]}),
             .sel(func[0] )),
arithMux(.out(arith ),
        .in0(shift ),
        .in1(add_sub),
        .sel(func[1])),
outMux(.out(out ),
      .in0(arith ),
      .in1(logic ),
      .sel(func[2]));
logic log( .out (logic ),
          .left (left ),
          .right (right ),
          .op (func[1:0]));
addSub addSub(.out (add_sub ),
             .cout (carryOut),
             .left (left ),
             .right (right ),
             .cin (carryIn ),
             .sub (func[0] ));

endmodule

module mux2(input sel ,
           input [31:0] in0, in1,
           output [31:0] out );
assign out = sel ? in1 : in0;
endmodule

module addSub(output [31:0] out ,
             output cout ,
             input [31:0] left, right ,
             input cin, sub );
assign {cout, out} = left + (right ^ {32{sub}}) + (cin ^ sub);
endmodule

module logic(output reg [31:0] out ,
            input [31:0] left, right ,
            input [1:0] op );
            integer i;
            wire [3:0] f;
assign f = {op[0], ~(~op[1] & op[0]), op[1], ~|op};
always @(left or right or f)
for(i=0; i<32; i=i+1) logicSlice(out[i], left[i], right[i], f);
task logicSlice;
output o;
input l, r;
input [3:0] f;
o = f[{l,r}];
endtask
endmodule