Verilog: How to use non--blocking instead of blocking statments?

Muralidhar Shenoy Guest 2013-05-03 02:32 #3150552

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I want to replace the blocking statements with non-blocking staements in 
the following code without changing the functionality of the code .

I am  newbie at verilog. can  someone please guide me on how to go ahead 
with this problem?

module q4(out ,in,clock,reset)
  output out ;
  input in,clock,reset ;
  reg out;
  reg[7:0] data;
  always @ (negedge reset of posedge clock) begin
    if (~reset) data = 8b'1111 1111;
    else begin 
      data = data << 1;
      data[0] = in;
      if(data == 8'b0111 1110) out = 1; else
        out = 0; end 


Thanks a lot! :)

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netseal Guest 2013-05-03 11:59 #3150837

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Hello,

in this code I can not see any statements, that could be paralelized 
without changing behavior.

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