Forum: FPGA, VHDL & Verilog Verilog: How to use non--blocking instead of blocking statments?

von Muralidhar Shenoy (Guest)

Rate this post
0 useful
not useful
I want to replace the blocking statements with non-blocking staements in 
the following code without changing the functionality of the code .

I am  newbie at verilog. can  someone please guide me on how to go ahead 
with this problem?
module q4(out ,in,clock,reset)
  output out ;
  input in,clock,reset ;
  reg out;
  reg[7:0] data;
  always @ (negedge reset of posedge clock) begin
    if (~reset) data = 8b'1111 1111;
    else begin 
      data = data << 1;
      data[0] = in;
      if(data == 8'b0111 1110) out = 1; else
        out = 0; end 

Thanks a lot! :)

von netseal (Guest)

Rate this post
0 useful
not useful

in this code I can not see any statements, that could be paralelized 
without changing behavior.


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.