I want to replace the blocking statements with non-blocking staements in the following code without changing the functionality of the code . I am newbie at verilog. can someone please guide me on how to go ahead with this problem?
1 | module q4(out ,in,clock,reset) |
2 | output out ; |
3 | input in,clock,reset ; |
4 | reg out; |
5 | reg[7:0] data; |
6 | always @ (negedge reset of posedge clock) begin |
7 | if (~reset) data = 8b'1111 1111; |
8 | else begin |
9 | data = data << 1; |
10 | data[0] = in; |
11 | if(data == 8'b0111 1110) out = 1; else |
12 | out = 0; end |
13 | end |
Thanks a lot! :)