vhdl accessing std_logic_vector

1

   Y <= "0000"; -- clear

2

-- DOESNT' WORK

3

  --Y(INDEX) <= E;

What doesn't work?
Does it not work when you uncomment the second assignment?
So, when you try at "first" clearing the vector and "afterwards" setting 
1 output bit?

> How can I access the output logic vector properly?
What do you want to do at all?

The error below occurs when I uncomment the section.
I just want to make sure that all other output bits are 0. I want to 
determine the index of the output bit position and therefore write one 
single bit into the vector at position INDEX.

> The error below occurs when I uncomment the section.
> I just want to make sure that all other output bits are 0.
You cannot do this (assigning two values to one signal) with a 
concurrent statement! Use a process instead:

1

  process (E, INDEX) begin

2

    Y <= "0000";      -- default assignment

3

    Y(INDEX) <= E;    -- "last" assignment "wins" 

4

  end process;

> the following example won't be compiled with gvhdl
A simulator should be able to handle this conflict. It must result in 
"X" values, but all in all the concurrent style code is able to be 
compiled...