Hi, the following example won't be compiled with gvhdl:
library ieee; use ieee.std_logic_1164.all; entity DemultiplexerEntity is port(E: in std_logic; SEL: in std_logic_vector(1 downto 0); Y: out std_logic_vector(3 downto 0) ); end DemultiplexerEntity; architecture DemultiplexerArchitectureSelektiv of DemultiplexerEntity is signal INDEX: integer; begin with SEL select INDEX <= 0 when "00", 1 when "01", 2 when "10", 3 when "11", 0 when others; Y <= "0000"; -- clear -- DOESNT' WORK --Y(INDEX) <= E; end DemultiplexerArchitectureSelektiv;
c++: test.cc: In member function ‘virtual bool L4work_E19demultiplexerentity_A33demultiplexerarchitectureselektiv_P4_7pn::execute()’: c++: test.cc:337:144: error: ‘L4work_E19demultiplexerentity_A33demultiplexerarchitectureselektiv_S5index’ was not declared in this scope
How can I access the output logic vector properly?
Y <= "0000"; -- clear -- DOESNT' WORK --Y(INDEX) <= E;
What doesn't work? Does it not work when you uncomment the second assignment? So, when you try at "first" clearing the vector and "afterwards" setting 1 output bit? > How can I access the output logic vector properly? What do you want to do at all?
The error below occurs when I uncomment the section. I just want to make sure that all other output bits are 0. I want to determine the index of the output bit position and therefore write one single bit into the vector at position INDEX.
> The error below occurs when I uncomment the section. > I just want to make sure that all other output bits are 0. You cannot do this (assigning two values to one signal) with a concurrent statement! Use a process instead:
process (E, INDEX) begin Y <= "0000"; -- default assignment Y(INDEX) <= E; -- "last" assignment "wins" end process;
> the following example won't be compiled with gvhdl A simulator should be able to handle this conflict. It must result in "X" values, but all in all the concurrent style code is able to be compiled...