hello all. please i need some help
i would like to display two images on a vga screen. and i'm using the
sdram to temporarely save frames before display. when i was using only
one image i didn't have any problem i had two write fifo and two read
fifo. but when i attempt to write/read another image means i added two
other FiFOs for the write and two other read Fifos for the read, i get a
mess on the vga display, knowing that i added a display module to decide
where to display the image since i divided the screen into 2. below is
an excerpt of the sdram control code
1
if (WR1_LOAD)
2
rWR1_ADDR <= WR1_ADDR;
3
else
4
if (mWR_DONE&&WR_MASK[0])
5
begin
6
if (rWR1_ADDR<WR1_MAX_ADDR-WR1_LENGTH)
7
rWR1_ADDR <= rWR1_ADDR+WR1_LENGTH;
8
else
9
rWR1_ADDR <= WR1_ADDR;
10
end
11
// Write Side 2
12
if (WR2_LOAD)
13
rWR2_ADDR <= WR2_ADDR;
14
else if (mWR_DONE&&WR_MASK[1])
15
begin
16
if (rWR2_ADDR<WR2_MAX_ADDR-WR2_LENGTH)
17
rWR2_ADDR <= rWR2_ADDR+WR2_LENGTH;
18
else
19
rWR2_ADDR <= WR2_ADDR;
20
end
21
// Write Side 3
22
if (WR3_LOAD)
23
rWR3_ADDR <= WR3_ADDR;
24
else
25
if (mWR_DONE&&WR_MASK[2])
26
begin
27
if (rWR3_ADDR<WR3_MAX_ADDR-WR3_LENGTH)
28
rWR3_ADDR <= rWR3_ADDR+WR3_LENGTH;
29
else
30
rWR3_ADDR <= WR3_ADDR;
31
end
32
// Write Side 4
33
if (WR4_LOAD)
34
rWR4_ADDR <= WR4_ADDR;
35
else if (mWR_DONE&&WR_MASK[3])
36
begin
37
if (rWR4_ADDR<WR4_MAX_ADDR-WR4_LENGTH)
38
rWR4_ADDR <= rWR4_ADDR+WR4_LENGTH;
39
else
40
rWR4_ADDR <= WR4_ADDR;
41
end
42
// Read Side 1
43
if (RD1_LOAD)
44
rRD1_ADDR <= RD1_ADDR;
45
else if (mRD_DONE&&RD_MASK[0])
46
begin
47
if (rRD1_ADDR<RD1_MAX_ADDR-RD1_LENGTH)
48
rRD1_ADDR <= rRD1_ADDR+RD1_LENGTH;
49
else
50
rRD1_ADDR <= RD1_ADDR;
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end
52
// Read Side 2
53
if (mRD_DONE&&RD_MASK[1])
54
begin
55
if (rRD2_ADDR<RD2_MAX_ADDR-RD2_LENGTH)
56
rRD2_ADDR <= rRD2_ADDR+RD2_LENGTH;
57
else
58
rRD2_ADDR <= RD2_ADDR;
59
end
60
// Read Side 3
61
if (RD3_LOAD)
62
rRD3_ADDR <= RD3_ADDR;
63
else if (mRD_DONE&&RD_MASK[2])
64
begin
65
if (rRD3_ADDR<RD3_MAX_ADDR-RD3_LENGTH)
66
rRD3_ADDR <= rRD3_ADDR+RD3_LENGTH;
67
else
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rRD3_ADDR <= RD3_ADDR;
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end
70
// Read Side 4
71
if (mRD_DONE&&RD_MASK[3])
72
begin
73
if (rRD4_ADDR<RD4_MAX_ADDR-RD4_LENGTH)
74
rRD4_ADDR <= rRD4_ADDR+RD4_LENGTH;
75
else
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rRD4_ADDR <= RD4_ADDR;
77
end
78
end
in the main program the sdram is mapped this way
1
Sdram_Control u7 ( // HOST Side
2
.RESET_N(KEY[0]),
3
.CLK(sdram_ctrl_clk),
4
5
// // FIFO Write Side 1
6
.WR1_DATA({1'b0,sCCD_G[11:7],sCCD_B[11:2]}),
7
.WR1(sCCD_DVAL),
8
.WR1_ADDR(0),
9
.WR1_MAX_ADDR(640*480/2),
10
.WR1_LENGTH(8'h50),
11
.WR1_LOAD(!DLY_RST_0),
12
.WR1_CLK(PIXCLK),
13
//
14
// // FIFO Write Side 2
15
.WR2_DATA({1'b0,sCCD_G[6:2],sCCD_R[11:2]}),
16
.WR2(sCCD_DVAL),
17
.WR2_ADDR(23'h25800),
18
19
.WR2_MAX_ADDR(23'h25800+640*480/2),
20
.WR2_LENGTH(8'h50),
21
.WR2_LOAD(!DLY_RST_0),
22
.WR2_CLK(PIXCLK),
23
24
//
25
// // FIFO Write Side 3
26
.WR3_DATA(data_test1),
27
.WR3(valid),
28
.WR3_ADDR(23'h60000),
29
.WR3_MAX_ADDR(23'h85800),
30
.WR3_LENGTH(8'h50),
31
.WR3_LOAD(!DLY_RST_0),
32
.WR3_CLK(PIXCLK),
33
//
34
// // FIFO Write Side 3
35
.WR4_DATA(data_test2),
36
.WR4(valid),
37
.WR4_ADDR(23'h90000),
38
.WR4_MAX_ADDR(23'h90000+640*480/2),
39
.WR4_LENGTH(8'h50),
40
.WR4_LOAD(!DLY_RST_0),
41
.WR4_CLK(PIXCLK),
42
43
// FIFO Read Side 1
44
.RD1_DATA(Read_DATA1),
45
.RD1(vga_read),
46
.RD1_ADDR(0),
47
.RD1_MAX_ADDR(640*480/2),
48
.RD1_LENGTH(8'h50),
49
.RD1_LOAD(!DLY_RST_0),
50
.RD1_CLK(~VGA_CTRL_CLK),
51
//
52
// // FIFO Read Side 2
53
.RD2_DATA(Read_DATA2),
54
.RD2(vga_read),
55
.RD2_ADDR(23'h25800),
56
.RD2_MAX_ADDR(23'h25800+640*480/2),
57
.RD2_LENGTH(8'h50),
58
.RD2_LOAD(!DLY_RST_0),
59
.RD2_CLK(~VGA_CTRL_CLK),
60
////
61
////// // FIFO Read Side 1
62
.RD3_DATA(Read_DATA3),
63
.RD3(vga_read),
64
.RD3_ADDR(23'h60000),
65
.RD3_MAX_ADDR(23'h85800),
66
.RD3_LENGTH(8'h50),
67
.RD3_LOAD(!DLY_RST_0),
68
.RD3_CLK(~VGA_CTRL_CLK),
69
////
70
// // FIFO Read Side 2
71
.RD4_DATA(Read_DATA4),
72
.RD4(vga_read),
73
.RD4_ADDR(23'h90000),
74
.RD4_MAX_ADDR(23'h90000+640*480/2),
75
.RD4_LENGTH(8'h50),
76
.RD4_LOAD(!DLY_RST_0),
77
.RD4_CLK(~VGA_CTRL_CLK),
78
79
// SDRAM Side
80
.SA(DRAM_ADDR),
81
.BA(DRAM_BA),
82
.CS_N(DRAM_CS_N),
83
.CKE(DRAM_CKE),
84
.RAS_N(DRAM_RAS_N),
85
.CAS_N(DRAM_CAS_N),
86
.WE_N(DRAM_WE_N),
87
.DQ(DRAM_DQ),
88
.DQM(DRAM_DQM)
89
);
i've a DE2-115 Board and i'm using quartus 10.0
Thank u
Hi Ladybird,
do u already solved your problem?
I also need to implement a controller of the sdram, but I have problems
to run it oin the board. May be we can change some ideas.
cheers, Dave
Maybe you sit done and write some block diagram first to show people
what you want to knwo and what you did? Nobody want's to guess it from a
non working code.