1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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4 |
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5 | entity rotaryEncoder is
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6 | Port (
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7 | clk : in STD_LOGIC; -- C9
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8 | RotA : in STD_LOGIC; -- K18 PULLUP
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9 | RotB : in STD_LOGIC; -- G18 PULLUP
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10 | data : inout STD_LOGIC_VECTOR(7 DOWNTO 0); -- E12
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11 | leds : inout STD_LOGIC_VECTOR(7 DOWNTO 0);
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12 | sout : inout std_logic;
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13 | sin : in std_logic);
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14 | end rotaryEncoder;
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15 |
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16 | architecture rotaryEncoder of rotaryEncoder is
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17 | signal sta : STD_LOGIC_VECTOR(1 downto 0);
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18 | signal prr : STD_LOGIC_vector(1 downto 0);
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19 | signal rotary_in : STD_LOGIC_vector(1 downto 0);
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20 | signal RotA1 : STD_LOGIC;
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21 | signal RotB1 : STD_LOGIC;
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22 | signal s1 :std_logic;
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23 | signal s2 :std_logic;
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24 | signal s3 :std_logic;
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25 | signal s4 :std_logic;
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26 | signal s5 :std_logic_vector(3 downto 0);
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27 | signal s6 :std_logic;
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28 | signal s7 :std_logic_vector(1 downto 0);
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29 | signal cmp :std_logic_vector(3 downto 0);
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30 | signal xcount3 : std_logic_vector(7 downto 0);
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31 | signal xcount1 : std_logic_vector(8 downto 0);
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32 | signal reg :std_logic_vector(7 downto 0);
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33 |
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34 | begin
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35 | rotary_filter:
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36 | process(clk)
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37 | begin
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38 | if clk'event and clk='1' then
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39 | rotary_in <= RotA & RotB;
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40 | case rotary_in is
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41 |
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42 | when "00" => RotA1 <= '0'; RotB1 <= RotB1;
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43 | when "01" => RotA1 <= RotA1; RotB1 <= '0';
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44 | when "10" => RotA1 <= RotA1; RotB1 <= '1';
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45 | when "11" => RotA1 <= '1'; RotB1 <= RotB1;
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46 | when others => RotA1 <= RotA1; RotB1 <= RotB1;
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47 | end case;
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48 | end if;
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49 | end process rotary_filter;
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50 |
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51 | direction:
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52 | process(clk) is begin
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53 | if(rising_edge(clk)) then
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54 | case sta & RotA1 & RotB1 is
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55 | when "0001" => prr <= "01"; sta <="01"; -- 01 turn right
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56 | when "0010" => prr <= "00"; sta <="10"; -- 00 turn left
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57 | when "0111" => prr <= "01"; sta <="11"; -- 10 null
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58 | when "0100" => prr <= "00"; sta <="00";
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59 | when "1000" => prr <= "10"; sta <="00";
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60 | when "1011" => prr <= "10"; sta <="11";
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61 | when "1110" => prr <= "10"; sta <="10";
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62 | when "1101" => prr <= "10"; sta <="01";
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63 | when others => null;
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64 | end case;
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65 | if(prr="00") then
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66 | data<=data+1; prr<="10";
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67 | elsif(prr="01") then
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68 | data<=data-1; prr<="10";
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69 | else
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70 | null;
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71 | end if;
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72 | end if;
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73 | end process;
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74 |
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75 | TRNS:process(clk) is begin
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76 | if clk'event and clk='1' then
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77 |
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78 | if(xcount1<="000000000") then
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79 | sout<='1';
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80 | elsif(xcount1="000000001") then
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81 | sout<='1';
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82 | elsif(xcount1="000000010") then
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83 | sout<='0';
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84 | elsif(xcount1="000000011") then
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85 | sout<='0';
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86 |
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87 | elsif((xcount1<=data)and(xcount1>"000000011")) then
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88 | sout<='1';
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89 | elsif(xcount1<="100000011") then
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90 | sout<='0';
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91 | elsif(xcount1="100000011") then
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92 | xcount1<="000000000";
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93 | end if;
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94 | xcount1<= xcount1 + 1;
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95 | end if;
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96 | end process;
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97 |
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98 | RCV:process(clk,sin,s1,s2,s3,s4,s5,s6,s7)is begin
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99 | if(rising_edge(clk)) then
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100 |
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101 | s1<=sin;
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102 | s2<=s1;
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103 | s3<=s2;
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104 | s4<=s3;
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105 | s5<=s1&s2&s3&s4;
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106 | s7<=s6&sin;
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107 | if(s5="0011") then
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108 | s6<='1';
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109 | end if;
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110 | if(s7="11") then
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111 |
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112 | leds<=leds;
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113 | reg<=xcount3;
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114 | else
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115 | leds<=reg-3;
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116 | end if;
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117 | xcount3<= xcount3 + 1;
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118 |
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119 | if(xcount3="11111111") then
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120 | xcount3<="00000000";
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121 | end if;
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122 | if(reg="11111111") then
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123 | reg<="00000000";
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124 | end if;
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125 | end if;
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126 | end process;
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127 | end rotaryEncoder;
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