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Forum: FPGA, VHDL & Verilog pwm modulation/demodulation


von alper y. (alperyazir)


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hi everyone. I need help about vhdl code of spartan3e.
i wanna communicate two FBGAs. For example, i am using rotary switch to 
produce pwm(it arranges my duty cycles. and i produce my pwm from my 1st 
FBGA and use it 2nd FBGA. i tried but it didnt happened.
please help me ??

my codes is:
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity rotaryEncoder is
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Port ( 
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      clk  : in    STD_LOGIC; -- C9
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      RotA : in    STD_LOGIC; -- K18 PULLUP
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      RotB : in    STD_LOGIC; -- G18 PULLUP
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      data : inout STD_LOGIC_VECTOR(7 DOWNTO 0); -- E12
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      leds : inout STD_LOGIC_VECTOR(7 DOWNTO 0);
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      sout : inout std_logic;
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      sin  : in std_logic);
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 end rotaryEncoder;
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 architecture rotaryEncoder of rotaryEncoder is
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 signal sta       : STD_LOGIC_VECTOR(1 downto 0);
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 signal prr       : STD_LOGIC_vector(1 downto 0);
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 signal rotary_in : STD_LOGIC_vector(1 downto 0);
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 signal RotA1     : STD_LOGIC;
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 signal RotB1     : STD_LOGIC;
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 signal s1        :std_logic;
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 signal s2        :std_logic;
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 signal s3        :std_logic;
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 signal s4        :std_logic;
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 signal s5        :std_logic_vector(3 downto 0);
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 signal s6        :std_logic;
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 signal s7        :std_logic_vector(1 downto 0);
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 signal cmp        :std_logic_vector(3 downto 0);
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 signal xcount3   : std_logic_vector(7 downto 0);
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 signal xcount1   : std_logic_vector(8 downto 0);
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 signal reg       :std_logic_vector(7 downto 0);
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 begin
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 rotary_filter: 
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 process(clk)    
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  begin                   
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    if clk'event and clk='1' then  
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    rotary_in <= RotA & RotB;      
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        case rotary_in is  
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          when "00" => RotA1 <= '0';     RotB1 <= RotB1;   
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          when "01" => RotA1 <= RotA1;   RotB1 <= '0';      
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          when "10" => RotA1 <= RotA1;   RotB1 <= '1';     
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          when "11" => RotA1 <= '1';     RotB1 <= RotB1;   
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          when others => RotA1 <= RotA1; RotB1 <= RotB1;                
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        end case;                    
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    end if;                        
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 end process rotary_filter;     
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 direction:
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  process(clk) is begin
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      if(rising_edge(clk)) then
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        case sta & RotA1 & RotB1 is
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    when "0001" => prr <= "01"; sta <="01"; -- 01 turn right
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          when "0010" => prr <= "00"; sta <="10"; -- 00 turn left
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    when "0111" => prr <= "01"; sta <="11"; -- 10 null
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    when "0100" => prr <= "00"; sta <="00";
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    when "1000" => prr <= "10"; sta <="00";
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    when "1011" => prr <= "10"; sta <="11";
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    when "1110" => prr <= "10"; sta <="10";
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    when "1101" => prr <= "10"; sta <="01";
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    when others => null;
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        end case;
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          if(prr="00") then
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            data<=data+1; prr<="10";
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          elsif(prr="01") then
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            data<=data-1; prr<="10";
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          else
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            null;
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          end if;
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       end if;
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   end process;
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  TRNS:process(clk) is begin 
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    if clk'event and clk='1' then
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        if(xcount1<="000000000") then
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        sout<='1';
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        elsif(xcount1="000000001") then
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        sout<='1';
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        elsif(xcount1="000000010") then
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        sout<='0';
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        elsif(xcount1="000000011") then
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        sout<='0';
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        elsif((xcount1<=data)and(xcount1>"000000011")) then
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            sout<='1';
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        elsif(xcount1<="100000011") then
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          sout<='0';
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        elsif(xcount1="100000011") then
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        xcount1<="000000000";  
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        end if;
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    xcount1<= xcount1 + 1;
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    end if;
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 end process;
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 RCV:process(clk,sin,s1,s2,s3,s4,s5,s6,s7)is begin
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       if(rising_edge(clk)) then
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          s1<=sin;
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         s2<=s1;
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         s3<=s2;
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         s4<=s3;
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          s5<=s1&s2&s3&s4;
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          s7<=s6&sin;
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         if(s5="0011") then
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        s6<='1';
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        end if;
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        if(s7="11") then
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            leds<=leds;
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            reg<=xcount3;
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        else
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            leds<=reg-3;
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        end if;
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        xcount3<= xcount3 + 1;
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        if(xcount3="11111111") then
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          xcount3<="00000000";
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        end if;
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         if(reg="11111111") then
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         reg<="00000000";
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         end if;
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      end if;
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    end process;
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 end rotaryEncoder;

von Lothar M. (lkmiller) (Moderator)


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Did you simulate your design? How does the testbench look like? And: 
what's the problem at all? What does not "happen"? What do you expect? 
And what do you get?

von Manni (Guest)


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I am again surprised, how complex a AB-decoding can be done. I never 
learned about that and therefor was very new to it, when I had to do it 
the first time. What I am doing:

I sample the incoming value with a frequency which is low enough, that 
bouncing has no effect anymore and decide, if the value changed. When it 
inreased or had an overrun, I am adding 1 to my result, in the other 
case i substracted one. Allways worked sufficiently.

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