Hi in VHDL language How to detect the concurrent occurrence of multiple signals in a process. an other word, is detected at a particular moment(same t) multiple signals have been activated simultaneously. please see the attached image. Thanks for your attention.
process(CLOCK) begin if (rising_edge(CLOCK)) then if ( a = '1' and a_old = '0' and b = '1' and b_old = '0' ) then -- Rising edge on a and b end if; a_old <= a; b_old <= b; end if; end process;
> How to detect the concurrent occurrence of multiple signals in a > process. It is not possible to detect an "edge" from 'U' uninitialized to '1' one. And if it may be, it makes no sense at all. Yor problem is somwhere else. So let me ask: What is your actual problem? How does the code look like?
my problem is: in a code I need that 5 process in architecture running. each process have one sensitivity list :req_rut1,req_rout2,...,req_rot5. if in a moment only one req_routi(i=1,...5) is activated no problem but if two or more req_routi are activated the problem is begun. there for I need that detect this time for solution and I prioritize them. edge from '0' to '1' is detectable?
> my problem is: > in a code I need that 5 process in architecture running. Your major problem is, that processes are not running! You have the wrong way of thinking! What you have here is hardware. All of your description is present and active, all the time. > edge from '0' to '1' is detectable? Yes, but not in your software based way of thingking. To detect an edge there must be a "before" and an "after". And so you will have to store something. And for storing something you need a flipflop. And a flipflop needs a clock. > if in a moment only one req_routi(i=1,...5) is activated no problem but > if two or more req_routi are activated the problem is begun. Which problem? With which code? (hmmm, didn't I ask this question not long ago?)
I've attached the code. in fact the requ_routi is clk for each process,because it move from '0' to '1',but irregular. Please see the code and the explain your solution. Thanks a lot. This forum very useful.
This process sensitivity list is incomplete:
process(req_rout1) begin if(req_rout1='1')then if(incoming1(3 downto 2)>ID(3 downto 2))then -- both of them are missing in the sensitivity list. if(free3='1')then -- and this also ... -- and so on, and on... process(req_rout3) begin if(req_rout3='1')then if(incoming3(3 downto 2)>ID(3 downto 2))then -- and the same here and further on...
A incomplete sensitivity list means that your simulation is just rubbish. Even if your design runs in simulation, the behaviour in reality will be completetly different, because the synthesizer doesn't use the sensitivity list at all! To keep things short: every signal that can change any output signal must be in the list. And becaus every if can change an output, every signal inside the if must be in the sensitivity list. BTW: vhdl files end with *.vhdl, not with *.txt
Sorry for attached file in .txt and Thanks for your explain. I have not seen this expline in any book. but my problem not solved! How detect the moment of activated 2 or more signals?(from '0' to '1')
> but my problem not solved! Of course not. But I cannot solve your problem, because I don't understaand your problem. > How detect the moment of activated 2 or more signals?(from '0' to '1') You want to "detect" the change of 2 signals at the very same moment? Or just "detect" the moment, when both signals are '1'? And what do you want to do after you "detected" this change? A very basic question: Do you really know, what VHDL is? It is a Hardware Description Language. So at first you must have a (at least a virtual) picture of the resulting hardware. Then you describe that function with VHDL. So: what would your hardware look like, when you were told to draw a schematic of it?
You're right, I did not think too much hardware, but I'm just learning. Thank you for taking the time. just "detect" the moment, when both or more signals are '1'. I make a decision after detect by "if".