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Hello all. I've been coding a Johnson Counter like the following:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity johnson is generic (n : natural := 4); port (clk, enable : in std_logic; count : out std_logic_vector (n-1 downto 0)); end johnson; architecture behavioural of johnson is signal reg_john, nxt_john : std_logic_vector (n-1 downto 0); begin process (clk) begin if (clk'event and clk='1') then if (enable='1') then reg_john<=nxt_john; end if; end if; end process; process (reg_john) begin nxt_john<=reg_john (n-2 downto 0) & not reg_john (n-1); end process; count<=reg_john; end behavioural; |
The synthetization was OK. The thing is when I tried to simulate the code, all the outputs from the count were having the letter 'U'. Please, take a look at the attached screenshot. Note that "habilitacion" = "enable" and "cuenta" = "count". What are those 'U's? How can I fix the simulation in order to work? Thanks a lot.
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'U' is the value for "uninitialized". Think about, at which value your counter starts. You can't determine is from the source code? So the simulator can't either! ;-) For the synthesiser, there is no value like 'U', only '0' and '1'. So it has to choose a value. Most likely it will use 0.
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Thanks Klaus, and I've also realized that the Xilinx Simulator has two kinds of options to simulate: "Behavioural Simulation" and "Post-Route Simulation", so I tried the last one in this case and it seemed to work.
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Both types of simulation will "work", if you just initialize the counters signal with (others =>'0') Don't work around some problem! Try to understand what's going on...
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Thank you very much, Lothar, you're right. I'm going to try it and see what happens. :)
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Here's the fixed Johnson Counter.