VHDL - Johnson Counter - Simulation Output with 'U's

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity johnson is

generic (n : natural := 4);

port (clk, enable : in std_logic;

      count : out std_logic_vector (n-1 downto 0));

end johnson;

architecture behavioural of johnson is

signal reg_john, nxt_john : std_logic_vector (n-1 downto 0);

begin

   process (clk)

   begin

      if (clk'event and clk='1') then

         if (enable='1') then

            reg_john<=nxt_john;

         end if;

      end if;

   end process;

   process (reg_john)

   begin

      nxt_john<=reg_john (n-2 downto 0) & not reg_john (n-1);

   end process;

   count<=reg_john;

end behavioural;