Hello all. I've been coding a Johnson Counter like the following:

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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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use IEEE.STD_LOGIC_ARITH.ALL;

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use IEEE.STD_LOGIC_UNSIGNED.ALL;

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entity johnson is

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generic (n : natural := 4);

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port (clk, enable : in std_logic;

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      count : out std_logic_vector (n-1 downto 0));

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end johnson;

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architecture behavioural of johnson is

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signal reg_john, nxt_john : std_logic_vector (n-1 downto 0);

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begin

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   process (clk)

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   begin

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      if (clk'event and clk='1') then

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         if (enable='1') then

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            reg_john<=nxt_john;

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         end if;

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      end if;

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   end process;

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   process (reg_john)

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   begin

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      nxt_john<=reg_john (n-2 downto 0) & not reg_john (n-1);

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   end process;

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   count<=reg_john;

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end behavioural;

The synthetization was OK. The thing is when I tried to simulate the 
code, all the outputs from the count were having the letter 'U'.

Please, take a look at the attached screenshot.

Note that "habilitacion" = "enable" and "cuenta" = "count".

What are those 'U's? How can I fix the simulation in order to work?

Thanks a lot.

Thanks Klaus, and I've also realized that the Xilinx Simulator has two 
kinds of options to simulate: "Behavioural Simulation" and "Post-Route 
Simulation", so I tried the last one in this case and it seemed to work.

Both types of simulation will "work", if you just initialize the 
counters signal with  (others =>'0')
Don't work around some problem! Try to understand what's going on...

Thank you very much, Lothar, you're right.

I'm going to try it and see what happens. :)

Here's the fixed Johnson Counter.