Hi I wrote a program that outputs it to me a little confused. So someone explain to me what the problem could be that I'm grateful. I'm going with the activation of a particular input to output transfer process sensitivity list for example if the active instance rx1 then in1 transferred to the output. The process for the first time about 10 times rx2 zero and one, respectively in2're just getting into the stream and no problem but In the second series, which began rx4 zero and one,and is repeated about 10 times over, the first valu of in4 not moved to output but later transferred to the output in4, respectively. please see the attached image. the process list sensitivity not have overlap. process(rx1,rx2,rx3,rx4,clk2) begin if(rx1='1')then ... ... elsif(rx2='1')then ... ... ... end if; end process;
> I wrote a program
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The problems in a VHDL code usually don't come from sensitivity lists.
In most cases they are buried somewhere else...
Hi It's hard to say what's going on without the sourcecode :/ Anyway, it looks like an standard flaw. The process sketch looks like a multiplexer. The process (in simulation) responds to all events of the signals in the sensitivity list. For a given time t assume two events in2 <= "FE", and rising_edge(rx2) in THAT order. The simulator assigns in2 and then to the neccassary action assigned to rx2 ( i expect this should be data_out <= in2. Thx for posting the code :-( ) So, after time t data_out is "FE". But if the (internal) event order is rising_edge(rx2) in2 <= "FE" then data_out is set (during the processing of the rx2 event) to the OLD value on in2 and THEN setting in2 to "FE". Since your process is not sensitive to changes in in2 the simulator has no reason to reevaluate the outputs of this process. Try adding the inx signals to the process. Then it should work, i.e: process(rx1,rx2,rx3,rx4,in1,in2,in3,in4) Regards Andreas
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