In this stupidly simple design i would expect to get around 50 flipflops
and a little bit glue logic. So all far, far away from your numbers!
1 | shared variable count_out : unsigned(9 downto 0) := (others => '0');
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Why the heck do you need a shared variable?
The first half year of your VHDL career you will not need ANY
variables at all!
1 | process(counter_in, rst)
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2 | begin
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3 | if(rst = '1') then
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4 | count_out := count;
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5 | count <= (others => '0');
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What should this do?
The sensitivity list is incomplete, because a change of count leads to
a change of count_out and therefore must lead to a recalculation of
this process.
And because of the list being incomplete your simulation is wrong.
1 | process(counter_in, rst)
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2 | begin
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3 | if(rst = '1') then
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4 | count_out := count;
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5 | elsif(rising_edge(counter_in)) then
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6 | -- do nothing with count_out
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7 | end if;
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8 | end process;
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Also this is a hidden latch on count_out. And thats a major mistake,
because for sure you do not need or even want a latch in this design.
As far as i see, you want to build a kind of a frequency or cycle
counter (how much cycles of counter_in in a certain time)?
How fast is or which frequency has counter_in?
I assume clk has 40MHz.
Then you count 1sec PLUS 25ns there:
1 | if waiting >= 40000000 then
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