Hey, guys! I work with the Quartus II (VHDL) and I see this error: "Error: Design contains 6912 blocks of type logic cell. However, device contains only 2910." And, if I remove the line "count_out: = count;" of the first process, the program is only 474 cells. You guys are my last hope! Help :* This is the code:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity counter_controller is port ( clk : in std_logic; info : in std_logic_vector(0 to 2); counter_in : in std_logic; counter_out : out std_logic_vector(9 downto 0) ); end counter_controller; architecture Behavioral of counter_controller is shared variable count_out : unsigned(9 downto 0) := (others => '0'); signal count : unsigned(9 downto 0) := (others => '0'); signal rst : std_logic := '0'; begin counter_out <= std_logic_vector(count_out); process(counter_in, rst) begin if(rst = '1') then count_out := count; count <= (others => '0'); elsif(rising_edge(counter_in)) then count <= count + 1; end if; end process; process(clk) variable waiting : natural := 0; variable sec : unsigned(5 downto 0) := (others => '0'); begin if rising_edge(clk) then if waiting >= 40000000 then if info(1) = '0' then rst <= '1'; waiting := 0; sec := (others => '0'); else if sec >= 45 then rst <= '1'; waiting := 0; sec := (others => '0'); else rst <= '0'; sec := sec + 1; end if; end if; else rst <= '0'; waiting := waiting + 1; end if; end if; end process; end Behavioral; |
Wow, I have never seen such a strange description of a counter. Is it youre first FPGA design? I think you should beginning with some basics. http://www.lothar-miller.de/s9y/categories/1-VHDL
In this stupidly simple design i would expect to get around 50 flipflops and a little bit glue logic. So all far, far away from your numbers!
shared variable count_out : unsigned(9 downto 0) := (others => '0'); |
Why the heck do you need a shared variable? The first half year of your VHDL career you will not need ANY variables at all!
process(counter_in, rst) begin if(rst = '1') then count_out := count; count <= (others => '0'); |
What should this do? The sensitivity list is incomplete, because a change of count leads to a change of count_out and therefore must lead to a recalculation of this process. And because of the list being incomplete your simulation is wrong.
process(counter_in, rst) begin if(rst = '1') then count_out := count; elsif(rising_edge(counter_in)) then -- do nothing with count_out end if; end process; |
Also this is a hidden latch on count_out. And thats a major mistake, because for sure you do not need or even want a latch in this design. As far as i see, you want to build a kind of a frequency or cycle counter (how much cycles of counter_in in a certain time)? How fast is or which frequency has counter_in? I assume clk has 40MHz. Then you count 1sec PLUS 25ns there:
if waiting >= 40000000 then
|
Sorry, guys, but I'm just learning. My task is to implement a count of pulses number from the input "counter_in" per second or per 45 seconds (depending on the input "info(1)"). As you have correctly understood, clk has 40MHz. Frequency from the input "counter_in" 5-50 Hz. I decided to write here, because a week can `t deal with this error. I tried to rewrite the code a few times ... Thanks for your response!
And, so.. Even this realization causes this error:
architecture Behavioral of counter_controller is signal count_out : unsigned(9 downto 0) := (others => '0'); signal count : unsigned(9 downto 0) := (others => '0'); signal rst : std_logic := '0'; begin counter_out <= std_logic_vector(count_out); rst <= info(0); process(counter_in, rst, count) begin if(rst = '1') then count_out <= count; count <= (others => '0'); elsif(rising_edge(counter_in)) then count <= count + 1; end if; end process; end Behavioral; |
where "info(0)" - switch.
> Even this realization causes this error: Which one? > Frequency from the input "counter_in" 5-50 Hz. Ok, so thats indeed not really a clock signal, but a slow input signal. (A beginners design must have only one clock, and thats the one from the crystal, here 40MHz) Now lets try it the new information in a new fashion:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity counter_controller is port ( clk : in std_logic; info : in std_logic_vector(0 to 2); counter_in : in std_logic; counter_out : out std_logic_vector(9 downto 0) ); end counter_controller; architecture Behavioral of counter_controller is signal c_in_sr : std_logic_vector(2 downto 0) := "000"; -- shift register for sync and edge detect signal c : integer range 0 to 50*45 := 0; -- the counter: 45sec with max. 50Hz signal onesec : integer range 0 to 40000000-1 := 0; signal sec : integer range 0 to 45-1 := 0; begin c_in_sr <= c_in_sr(1 downto 0) & counter_in when rising_edge(clk); -- syncchronize the input signal process begin wait until rising_edge(clk); if (c_in_sr(2 downto 1) = "01") then -- detect rising edge of input signal c <= c+1; -- and count the rising edges end if; if (onesec < 40000000-1) then -- count for one second onesec <= onesec+1; else onesec <= 0; if (info(1) = '0') then -- sample counter every second counter_out <= std_logic_vector(to_unsigned(c,10)); c <= 0; sec <= 0; else -- sample counter every 45 seconds if (sec < 45-1) then -- count 45 seconds sec <= sec+1; else counter_out <= std_logic_vector(to_unsigned(c,10)); c <= 0; sec <= 0; end if; end if; end if; end process; end Behavioral; |
Oh, this code produces the same error :( I don't understand what the problem is. By the way, I use the Quartus and Cyclone FPGA.
I have no experience with Quartus, but with Xilinx ISE i get: Number of Slices 37 Number of Slice Flip Flops 54 (a few posts above i expected 50) Number of 4 input LUTs 61 And thats a fairly small design. I assume there is something wrong in the project settings in your design.
I ran Lothars code through QuartusII 12.1 for a CycloneIV. I get a Resource Utilization for the counter_controller entity of 69 Logic Cells and 43 LUT/Register LCs. Seems fine for me. Dasiy-Cat, did you try Lothars code?
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