Error: Not enough of logic cells.

Daisy-Cat Guest #2947719
Rate this post
• ▲ useful
▼ not useful 
Hey, guys!
I work with the Quartus II (VHDL) and I see this error: "Error: Design 
contains 6912 blocks of type logic cell.  However, device contains only 
2910."

And, if I remove the line "count_out: = count;" of the first process, 
the program is only 474 cells.

You guys are my last hope! Help :*

This is the code:

1
library IEEE;

2
use IEEE.STD_LOGIC_1164.ALL;

3
use IEEE.NUMERIC_STD.ALL;

4


5
entity counter_controller is

6


7
  port (

8
    clk          : in   std_logic;

9
    info      : in   std_logic_vector(0 to 2);

10
    counter_in    : in   std_logic;

11
    counter_out    : out  std_logic_vector(9 downto 0)

12
  );

13


14
end counter_controller;

15


16
architecture Behavioral of counter_controller is

17
  

18
  shared variable count_out  : unsigned(9 downto 0)   := (others => '0');

19
  signal count    : unsigned(9 downto 0)   := (others => '0');

20
  signal rst       : std_logic := '0';

21
  

22
begin

23
  

24
  counter_out <= std_logic_vector(count_out);

25
  

26
  process(counter_in, rst)

27
  begin

28
    if(rst = '1') then

29
      count_out := count;

30
      count <= (others => '0');

31
    elsif(rising_edge(counter_in)) then

32
      count <= count + 1;

33
    end if;

34
  end process;

35


36
  process(clk)

37
    variable waiting  : natural         := 0;

38
    variable sec    : unsigned(5 downto 0)  := (others => '0');

39
  begin

40
    if rising_edge(clk) then

41
      if waiting >= 40000000 then

42
        if info(1) = '0' then

43
          rst <= '1';

44
          waiting := 0;

45
          sec := (others => '0');

46
        else

47
          if sec >= 45 then

48
            rst <= '1';

49
            waiting := 0;

50
            sec := (others => '0');

51
          else

52
            rst <= '0';

53
            sec := sec + 1;

54
          end if;

55
        end if;

56
      else

57
        rst <= '0';

58
        waiting := waiting + 1;

59
      end if;

60
    end if;

61
  end process;

62
  

63
end Behavioral;
Reply Quote Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Report post
Lothar M. Moderator (Company: Titel) #2947886
Rate this post
• ▲ useful
▼ not useful 
In this stupidly simple design i would expect to get around 50 flipflops 
and a little bit glue logic. So all far, far away from your numbers!

1
  shared variable count_out  : unsigned(9 downto 0)   := (others => '0');

Why the heck do you need a shared variable?
The first half year of your VHDL career you will not need ANY 
variables at all!

1
  process(counter_in, rst)

2
  begin

3
    if(rst = '1') then

4
      count_out := count;

5
      count <= (others => '0');

What should this do?
The sensitivity list is incomplete, because a change of count leads to 
a change of count_out and therefore must lead to a recalculation of 
this process.
And because of the list being incomplete your simulation is wrong.

1
  process(counter_in, rst)

2
  begin

3
    if(rst = '1') then

4
      count_out := count;

5
    elsif(rising_edge(counter_in)) then

6
      -- do nothing with count_out

7
    end if;

8
  end process;

Also this is a hidden latch on count_out. And thats a major mistake, 
because for sure you do not need or even want a latch in this design.

As far as i see, you want to build a kind of a frequency or cycle 
counter (how much cycles of counter_in in a certain time)?
How fast is or which frequency has counter_in?
I assume clk has 40MHz.
Then you count 1sec PLUS 25ns there:
1
      if waiting >= 40000000 then
Reply Quote Edit Delete Report post
Daisy-Cat Guest #2947894
Rate this post
• ▲ useful
▼ not useful 
Sorry, guys, but I'm just learning.
My task is to implement a count of pulses number from the input 
"counter_in" per second or per 45 seconds (depending on the input 
"info(1)").
As you have correctly understood, clk has 40MHz. Frequency from the 
input "counter_in" 5-50 Hz.
I decided to write here, because a week can `t deal with this error. I 
tried to rewrite the code a few times ...

Thanks for your response!
Reply Quote Edit Delete Report post
Daisy-Cat Guest #2947913
Rate this post
• ▲ useful
▼ not useful 
And, so.. Even this realization causes this error:

1
architecture Behavioral of counter_controller is

2
  

3
  signal count_out  : unsigned(9 downto 0)   := (others => '0');

4
  signal count      : unsigned(9 downto 0)   := (others => '0');

5
  signal rst         : std_logic := '0';

6
  

7
begin

8
  

9
  counter_out <= std_logic_vector(count_out);

10
  

11
  rst <= info(0);

12
  

13
  process(counter_in, rst, count)

14
  begin

15
    if(rst = '1') then

16
    count_out <= count;

17
    count <= (others => '0');

18
    elsif(rising_edge(counter_in)) then

19
    count <= count + 1;

20
    end if;

21
  end process;

22
  

23
end Behavioral;


where "info(0)" - switch.
Reply Quote Edit Delete Report post
Lothar M. Moderator (Company: Titel) #2947962
Rate this post
• ▲ useful
▼ not useful 
>  Even this realization causes this error:
Which one?

> Frequency from the input "counter_in" 5-50 Hz.
Ok, so thats indeed not really a clock signal, but a slow input signal.
(A beginners design must have only one clock, and thats the one from 
the crystal, here 40MHz)


Now lets try it the new information in a new fashion:
1
library IEEE;

2
use IEEE.STD_LOGIC_1164.ALL;

3
use IEEE.NUMERIC_STD.ALL;

4


5
entity counter_controller is

6


7
  port (

8
    clk           : in   std_logic;

9
    info          : in   std_logic_vector(0 to 2);

10
    counter_in    : in   std_logic;

11
    counter_out   : out  std_logic_vector(9 downto 0)

12
  );

13


14
end counter_controller;

15


16
architecture Behavioral of counter_controller is

17
  

18
  signal c_in_sr    : std_logic_vector(2 downto 0) := "000"; -- shift register for sync and edge detect

19
  signal c          : integer range 0 to 50*45 := 0;         -- the counter: 45sec with max. 50Hz

20
  signal onesec     : integer range 0 to 40000000-1 := 0;

21
  signal sec        : integer range 0 to 45-1       := 0;

22


23
begin

24


25
  c_in_sr <= c_in_sr(1 downto 0) & counter_in when rising_edge(clk); -- syncchronize the input signal

26
  

27
  process begin

28
    wait until rising_edge(clk);

29
    if (c_in_sr(2 downto 1) = "01") then -- detect rising edge of input signal

30
       c <= c+1;                         -- and count the rising edges

31
    end if;

32


33
    if (onesec < 40000000-1) then  -- count for one second

34
      onesec <= onesec+1;

35
    else

36
      onesec <= 0;

37
      if (info(1) = '0') then     -- sample counter every second

38
        counter_out <= std_logic_vector(to_unsigned(c,10));

39
        c     <= 0;

40
        sec   <= 0;

41
      else                        -- sample counter every 45 seconds

42
        if (sec < 45-1) then      -- count 45 seconds

43
          sec <= sec+1;

44
        else

45
          counter_out <= std_logic_vector(to_unsigned(c,10));

46
          c     <= 0;

47
          sec   <= 0;

48
        end if;

49
      end if;

50
    end if;

51
  end process;

52
  

53
end Behavioral;
Reply Quote Edit Delete Report post
Lothar M. Moderator (Company: Titel) #2948024
Rate this post
• ▲ useful
▼ not useful 
I have no experience with Quartus, but with Xilinx ISE i get:
Number of Slices 37
Number of Slice Flip Flops 54  (a few posts above i expected 50)
Number of 4 input LUTs 61
And thats a fairly small design.

I assume there is something wrong in the project settings in your 
design.
Reply Quote Edit Delete Report post
Watch this topic

Reply

Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.

Formatting
  • [c]C-Code[/c]
  • [vhdl]VHDL-Code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]
  • [[Title]] – link to an article
  • Link to another post: right-click its post ID (#8078628), copy the address, paste it into the text

More about formatting

Post long source code as an attachment, not in the text.

Your name and e-mail address

Already registered? Log in

Not shown to anyone. We send you a link; your post appears once you confirm it there.

By submitting you create a free account and accept the terms of use.