Hi how can the sinsivty list in process be independent from each other? for a example in process(clk1,clk2) a piece of process not run when change clk1. the Rising_edge(clk1) or clk1'event not useful,because they can be used only once. this is wrong: --=========== process(clk1,clk2) begin if(rising_edge(clk1))then out1<=a; . . . end if; if(rising_edge(clk2))then out1<=b; . . . end if; end process; --=========== I wrote my own code in Xilinx7 and Xilinx12. the error message this: "signal out1 can not be synthesized, bad synchronous description". Thanks for your attention
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#2940009
heeehhh?
The actual problem is: out1 is a flipflop. That's a fact, because any component reacting to an signals edge will result in a flipflop. And then: there are no "dual clock input" flipflops in the world. Why do you need two clocks in your design? A beginners design has exactly 1 clock all over the FPGA.
thanks a lot, I realized what my problem was.