Forum: FPGA, VHDL & Verilog [begginer issue] Read and Write to txt files

von Charalampos O. (Company: iiu) (haorfani)

Attached files:
  • 1.txt (18 Bytes, 296 downloads)

Rate this post
0 useful
not useful
Hello everyone I am new to vhdl so am having trouble to do simple things 
such as reading and writing from txt files.My problem with the following 
code is that all I am taking is an empty txt file.Is there any way to 
check my variables if they are empty or not?

I ve also uploaded the input file
--include this library for file handling in VHDL.
library std;
use std.textio.all;  --include package textio.vhd

--entity declaration
entity filehandle is
end filehandle;

--architecture definition
architecture Behavioral of filehandle is
--period of clock,bit for indicating end of file.
signal clock,endoffile : bit := '0';
--data read from the file.
signal    dataread : real;
--data to be saved into the output file.
signal    datatosave : real;
--line number of the file read or written.
signal    linenumber : integer:=1; 


clock <= not (clock) after 1 ns;    --clock with time period 2 ns

--read process
reading :
    file   infile    : text is in  "C:\Users\Deton@tor\Documents\02217 Design of Arithmetic Processors\aes\1.txt";   --declare input file
    variable  inline    : line; --line number declaration
    variable  dataread1    : real;

wait until clock = '1' and clock'event;
if (not endfile(infile)) then   --checking the "END OF FILE" is not reached.
readline(infile, inline);       --reading a line from the file.
  --reading the data from the line and putting it in a real type variable.
read(inline, dataread1);

dataread <=dataread1;   --put the value available in variable in a signal.
endoffile <='1';         --set signal to tell end of file read file is reached.
end if;

end process reading;

--write process
writing :
    file      outfile  : text is out "C:\Users\Deton@tor\Documents\02217 Design of Arithmetic Processors\aes\2.txt";  --declare output file
    variable  outline  : line;   --line number declaration  
wait until clock = '0' and clock'event;
if(endoffile='0') then   --if the file end is not reached.
--write(linenumber,value(real type),justified(side),field(width),digits(natural));
write(outline, dataread, right, 16, 12);
-- write line to external file.
writeline(outfile, outline);
linenumber <= linenumber + 1;
end if;

end process writing;

end Behavioral;

von René D. (Company: www.dossmatik.de) (dose)

Rate this post
0 useful
not useful
> signal    dataread : real;

I am not the expert in read/write in VDHL.

But I think the dataformat real in files is not a standard.
You file 1.txt is an ascii file. You have to convert ascii to real.

von Fetz (Guest)

Rate this post
0 useful
not useful
I would have a bad feeling using filenames or paths with a '@' in it ...

But that's the youth ... They weren't punished like we were 20yrs ago :D


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.