Hello everyone I am new to vhdl so am having trouble to do simple things
such as reading and writing from txt files.My problem with the following
code is that all I am taking is an empty txt file.Is there any way to
check my variables if they are empty or not?
I ve also uploaded the input file
--include this library for file handling in VHDL.
use std.textio.all; --include package textio.vhd
entity filehandle is
architecture Behavioral of filehandle is
--period of clock,bit for indicating end of file.
signal clock,endoffile : bit := '0';
--data read from the file.
signal dataread : real;
--data to be saved into the output file.
signal datatosave : real;
--line number of the file read or written.
signal linenumber : integer:=1;
clock <= not (clock) after 1 ns; --clock with time period 2 ns
file infile : text is in "C:\Users\Deton@tor\Documents\02217 Design of Arithmetic Processors\aes\1.txt"; --declare input file
variable inline : line; --line number declaration
variable dataread1 : real;
wait until clock = '1' and clock'event;
if (not endfile(infile)) then --checking the "END OF FILE" is not reached.
readline(infile, inline); --reading a line from the file.
--reading the data from the line and putting it in a real type variable.
dataread <=dataread1; --put the value available in variable in a signal.
endoffile <='1'; --set signal to tell end of file read file is reached.
end process reading;
file outfile : text is out "C:\Users\Deton@tor\Documents\02217 Design of Arithmetic Processors\aes\2.txt"; --declare output file
variable outline : line; --line number declaration
wait until clock = '0' and clock'event;
if(endoffile='0') then --if the file end is not reached.
write(outline, dataread, right, 16, 12);
-- write line to external file.
linenumber <= linenumber + 1;
end process writing;