hi... i want to design FSM with to two clocks in vhdl. i want to include in y program clock divider. so my prosesing of program can be fast at input. slow at display output.. can u help me? how design it in vhdl?
If you want to make your design work properly on a real target and if you are not really familiar with VHDL, constraining, clock domains etc you will run into big shit, if you try it this way.. Which clock rates do you intend to have on your design?
> i want to design FSM with to two clocks in vhdl. Pls. show in a short sample code how this should work. Do you know, how FSM are implemented on hardware? > so my prosesing of program can be fast at input. > slow at display output. What is "input"? What is "fast"? What "display"? What is "slow"? What do you want to do? > can u help me? Not until much more details are known. What is connected to "the FSM"? What function must be implemented in "the FSM"? All in all: Usually if one has a problem and one does't find a almost similar solution, then one is on the wrong way. And I never saw a FSM with two clocks...
clock input in FSM architecture divided by two..example one clock for 10khz frequency and others 1hz frequency..so i can to select one of two clock for delaying display of 7 segment, cause if i use counter, i will count more value for looping ..like counter in microcontroller...
If you want to "slow down" some functionality in your design you shall not divide the clock or worse: switch between different clocks! You use a single system clock (fast) and you generate different slower enable-signals via counter derived form this system clock via counter an comparator. With this enable-signals the slower functionality ist enabled (or disabled)
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